1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright 2022-2023 NXP 4 */ 5 6 #include <assert.h> 7 #include <compiler.h> 8 #include <config.h> 9 #include <console.h> 10 #include <keep.h> 11 #include <kernel/boot.h> 12 #include <kernel/linker.h> 13 #include <kernel/misc.h> 14 #include <kernel/panic.h> 15 #include <kernel/thread.h> 16 #include <mm/core_memprot.h> 17 #include <mm/core_mmu.h> 18 #include <mm/tee_mm.h> 19 #include <mm/tee_pager.h> 20 #include <platform_config.h> 21 #include <riscv.h> 22 #include <sbi.h> 23 #include <stdio.h> 24 #include <trace.h> 25 #include <util.h> 26 27 #define PADDR_INVALID ULONG_MAX 28 29 paddr_t start_addr; 30 unsigned long boot_args[4]; 31 32 uint32_t sem_cpu_sync[CFG_TEE_CORE_NB_CORE]; 33 34 void init_sec_mon(unsigned long nsec_entry __maybe_unused) 35 { 36 assert(nsec_entry == PADDR_INVALID); 37 /* Do nothing as we don't have a secure monitor */ 38 } 39 40 #ifdef CFG_RISCV_S_MODE 41 static void start_secondary_cores(void) 42 { 43 size_t i = 0; 44 size_t pos = get_core_pos(); 45 46 for (i = 0; i < CFG_TEE_CORE_NB_CORE; i++) 47 if (i != pos && IS_ENABLED(CFG_RISCV_SBI) && 48 sbi_boot_hart(i, start_addr, i)) 49 EMSG("Error starting secondary hart %zu", i); 50 } 51 #endif 52 53 static void init_runtime(void) 54 { 55 malloc_add_pool(__heap1_start, __heap1_end - __heap1_start); 56 57 IMSG_RAW("\n"); 58 } 59 60 void init_tee_runtime(void) 61 { 62 core_mmu_init_ta_ram(); 63 call_preinitcalls(); 64 call_initcalls(); 65 } 66 67 static void init_primary(unsigned long nsec_entry) 68 { 69 /* 70 * Mask asynchronous exceptions before switch to the thread vector 71 * as the thread handler requires those to be masked while 72 * executing with the temporary stack. The thread subsystem also 73 * asserts that the foreign interrupts are blocked when using most of 74 * its functions. 75 */ 76 thread_set_exceptions(THREAD_EXCP_ALL); 77 78 init_runtime(); 79 thread_init_boot_thread(); 80 thread_init_primary(); 81 thread_init_per_cpu(); 82 init_sec_mon(nsec_entry); 83 } 84 85 /* May be overridden in plat-$(PLATFORM)/main.c */ 86 __weak void plat_primary_init_early(void) 87 { 88 } 89 90 /* May be overridden in plat-$(PLATFORM)/main.c */ 91 __weak void main_init_plic(void) 92 { 93 } 94 95 /* May be overridden in plat-$(PLATFORM)/main.c */ 96 __weak void main_secondary_init_plic(void) 97 { 98 } 99 100 void boot_init_primary_early(unsigned long pageable_part __unused, 101 unsigned long nsec_entry __unused) 102 { 103 unsigned long e = PADDR_INVALID; 104 105 init_primary(e); 106 } 107 108 void boot_init_primary_late(unsigned long fdt __unused) 109 { 110 IMSG("OP-TEE version: %s", core_v_str); 111 if (IS_ENABLED(CFG_WARN_INSECURE)) { 112 IMSG("WARNING: This OP-TEE configuration might be insecure!"); 113 IMSG("WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html"); 114 } 115 IMSG("Primary CPU initializing"); 116 main_init_plic(); 117 init_tee_runtime(); 118 call_finalcalls(); 119 IMSG("Primary CPU initialized"); 120 121 #ifdef CFG_RISCV_S_MODE 122 start_secondary_cores(); 123 #endif 124 } 125 126 static void init_secondary_helper(unsigned long nsec_entry) 127 { 128 size_t pos = get_core_pos(); 129 130 IMSG("Secondary CPU %zu initializing", pos); 131 132 /* 133 * Mask asynchronous exceptions before switch to the thread vector 134 * as the thread handler requires those to be masked while 135 * executing with the temporary stack. The thread subsystem also 136 * asserts that the foreign interrupts are blocked when using most of 137 * its functions. 138 */ 139 thread_set_exceptions(THREAD_EXCP_ALL); 140 141 thread_init_per_cpu(); 142 init_sec_mon(nsec_entry); 143 main_secondary_init_plic(); 144 145 IMSG("Secondary CPU %zu initialized", pos); 146 } 147 148 void boot_init_secondary(unsigned long nsec_entry __unused) 149 { 150 init_secondary_helper(PADDR_INVALID); 151 } 152