1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2023 Andes Technology Corporation 4 * Copyright 2022-2023 NXP 5 */ 6 7 #include <assert.h> 8 #include <compiler.h> 9 #include <config.h> 10 #include <console.h> 11 #include <keep.h> 12 #include <kernel/boot.h> 13 #include <kernel/dt.h> 14 #include <kernel/linker.h> 15 #include <kernel/misc.h> 16 #include <kernel/panic.h> 17 #include <kernel/thread.h> 18 #include <libfdt.h> 19 #include <mm/core_memprot.h> 20 #include <mm/core_mmu.h> 21 #include <mm/tee_mm.h> 22 #include <mm/tee_pager.h> 23 #include <platform_config.h> 24 #include <riscv.h> 25 #include <sbi.h> 26 #include <stdio.h> 27 #include <trace.h> 28 #include <util.h> 29 30 #define PADDR_INVALID ULONG_MAX 31 32 paddr_t start_addr; 33 34 uint32_t sem_cpu_sync[CFG_TEE_CORE_NB_CORE]; 35 uint32_t hartids[CFG_TEE_CORE_NB_CORE]; 36 37 #if defined(CFG_DT) 38 static int mark_tddram_as_reserved(struct dt_descriptor *dt) 39 { 40 return add_res_mem_dt_node(dt, "optee_core", CFG_TDDRAM_START, 41 CFG_TDDRAM_SIZE); 42 } 43 44 static void update_external_dt(void) 45 { 46 struct dt_descriptor *dt = get_external_dt_desc(); 47 48 if (!dt || !dt->blob) 49 return; 50 51 #ifdef CFG_CORE_RESERVED_SHM 52 if (mark_static_shm_as_reserved(dt)) 53 panic("Failed to config non-secure memory"); 54 #endif 55 56 if (mark_tddram_as_reserved(dt)) 57 panic("Failed to config secure memory"); 58 } 59 #else /*CFG_DT*/ 60 static void update_external_dt(void) 61 { 62 } 63 #endif /*!CFG_DT*/ 64 65 void init_sec_mon(unsigned long nsec_entry __maybe_unused) 66 { 67 assert(nsec_entry == PADDR_INVALID); 68 /* Do nothing as we don't have a secure monitor */ 69 } 70 71 #ifdef CFG_RISCV_S_MODE 72 static void start_secondary_cores(void) 73 { 74 uint32_t curr_hartid = thread_get_core_local()->hart_id; 75 enum sbi_hsm_hart_state status = 0; 76 uint32_t hartid = 0; 77 int rc = 0; 78 int i = 0; 79 80 /* The primary CPU is always indexed by 0 */ 81 assert(get_core_pos() == 0); 82 83 for (i = 0; i < CFG_TEE_CORE_NB_CORE; i++) { 84 hartid = hartids[i]; 85 86 if (hartid == curr_hartid) 87 continue; 88 89 rc = sbi_hsm_hart_get_status(hartid, &status); 90 /* 91 * Skip if the hartid is not an assigned hart 92 * of the trusted domain, or its HSM state is 93 * not stopped. 94 */ 95 if (rc || status != SBI_HSM_STATE_STOPPED) 96 continue; 97 98 DMSG("Bringing up secondary hart%"PRIu32, hartid); 99 100 rc = sbi_hsm_hart_start(hartid, start_addr, 0 /* unused */); 101 if (rc) { 102 EMSG("Error starting secondary hart%"PRIu32, hartid); 103 panic(); 104 } 105 } 106 } 107 #endif 108 109 void init_tee_runtime(void) 110 { 111 call_preinitcalls(); 112 call_early_initcalls(); 113 call_service_initcalls(); 114 } 115 116 static bool add_padding_to_pool(vaddr_t va, size_t len, void *ptr __unused) 117 { 118 malloc_add_pool((void *)va, len); 119 return true; 120 } 121 122 static void init_primary(unsigned long nsec_entry) 123 { 124 vaddr_t va __maybe_unused = 0; 125 126 thread_init_core_local_stacks(); 127 128 /* 129 * Mask asynchronous exceptions before switch to the thread vector 130 * as the thread handler requires those to be masked while 131 * executing with the temporary stack. The thread subsystem also 132 * asserts that the foreign interrupts are blocked when using most of 133 * its functions. 134 */ 135 thread_set_exceptions(THREAD_EXCP_ALL); 136 137 malloc_add_pool(__heap1_start, __heap1_end - __heap1_start); 138 IMSG_RAW("\n"); 139 140 core_mmu_save_mem_map(); 141 core_mmu_init_phys_mem(); 142 boot_mem_foreach_padding(add_padding_to_pool, NULL); 143 va = boot_mem_release_unused(); 144 145 thread_init_boot_thread(); 146 thread_init_primary(); 147 thread_init_per_cpu(); 148 init_sec_mon(nsec_entry); 149 } 150 151 /* May be overridden in plat-$(PLATFORM)/main.c */ 152 __weak void plat_primary_init_early(void) 153 { 154 } 155 156 /* May be overridden in plat-$(PLATFORM)/main.c */ 157 __weak void boot_primary_init_intc(void) 158 { 159 } 160 161 /* May be overridden in plat-$(PLATFORM)/main.c */ 162 __weak void boot_primary_init_core_ids(void) 163 { 164 #ifdef CFG_DT 165 const void *fdt = get_external_dt(); 166 const fdt32_t *reg = NULL; 167 int cpu_offset = 0; 168 int offset = 0; 169 int len = 0; 170 int i = 0; 171 172 offset = fdt_path_offset(fdt, "/cpus"); 173 if (offset < 0) 174 panic("Failed to find /cpus node in the device tree"); 175 176 fdt_for_each_subnode(cpu_offset, fdt, offset) { 177 /* 178 * Assume all TEE cores are enabled. The "reg" 179 * property in the CPU node indicates the hart ID. 180 */ 181 if (fdt_get_status(fdt, cpu_offset) == DT_STATUS_DISABLED) 182 continue; 183 184 reg = fdt_getprop(fdt, cpu_offset, "reg", &len); 185 if (!reg) { 186 EMSG("CPU node does not have 'reg' property"); 187 continue; 188 } 189 190 assert(i < CFG_TEE_CORE_NB_CORE); 191 hartids[i++] = fdt32_to_cpu(*reg); 192 } 193 194 assert(i == CFG_TEE_CORE_NB_CORE); 195 #endif 196 } 197 198 /* May be overridden in plat-$(PLATFORM)/main.c */ 199 __weak void boot_secondary_init_intc(void) 200 { 201 } 202 203 void boot_init_primary_early(void) 204 { 205 unsigned long e = PADDR_INVALID; 206 207 init_primary(e); 208 } 209 210 void boot_init_primary_late(unsigned long fdt, 211 unsigned long tos_fw_config __unused) 212 { 213 size_t pos = get_core_pos(); 214 215 /* The primary CPU is always indexed by 0 */ 216 assert(pos == 0); 217 218 init_external_dt(fdt, CFG_DTB_MAX_SIZE); 219 discover_nsec_memory(); 220 update_external_dt(); 221 222 IMSG("OP-TEE version: %s", core_v_str); 223 if (IS_ENABLED(CFG_INSECURE)) { 224 IMSG("WARNING: This OP-TEE configuration might be insecure!"); 225 IMSG("WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html"); 226 } 227 IMSG("Primary CPU0 (hart%"PRIu32") initializing", 228 thread_get_hartid_by_hartindex(pos)); 229 boot_primary_init_intc(); 230 boot_primary_init_core_ids(); 231 init_tee_runtime(); 232 } 233 234 void __weak boot_init_primary_final(void) 235 { 236 size_t pos = get_core_pos(); 237 238 boot_mem_release_tmp_alloc(); 239 240 call_driver_initcalls(); 241 call_finalcalls(); 242 IMSG("Primary CPU0 (hart%"PRIu32") initialized", 243 thread_get_hartid_by_hartindex(pos)); 244 245 #ifdef CFG_RISCV_S_MODE 246 start_secondary_cores(); 247 #endif 248 } 249 250 static void init_secondary_helper(unsigned long nsec_entry) 251 { 252 size_t pos = get_core_pos(); 253 254 IMSG("Secondary CPU%zu (hart%"PRIu32") initializing", 255 pos, thread_get_hartid_by_hartindex(pos)); 256 257 /* 258 * Mask asynchronous exceptions before switch to the thread vector 259 * as the thread handler requires those to be masked while 260 * executing with the temporary stack. The thread subsystem also 261 * asserts that the foreign interrupts are blocked when using most of 262 * its functions. 263 */ 264 thread_set_exceptions(THREAD_EXCP_ALL); 265 266 thread_init_per_cpu(); 267 init_sec_mon(nsec_entry); 268 boot_secondary_init_intc(); 269 270 IMSG("Secondary CPU%zu (hart%"PRIu32") initialized", 271 pos, thread_get_hartid_by_hartindex(pos)); 272 } 273 274 void boot_init_secondary(unsigned long nsec_entry __unused) 275 { 276 init_secondary_helper(PADDR_INVALID); 277 } 278