1*380907c9SMarouene Boubakri /* SPDX-License-Identifier: BSD-2-Clause */ 2*380907c9SMarouene Boubakri /* 3*380907c9SMarouene Boubakri * Copyright 2022-2023 NXP 4*380907c9SMarouene Boubakri */ 5*380907c9SMarouene Boubakri 6*380907c9SMarouene Boubakri #ifndef __KERNEL_CLINT_H 7*380907c9SMarouene Boubakri #define __KERNEL_CLINT_H 8*380907c9SMarouene Boubakri 9*380907c9SMarouene Boubakri #include <io.h> 10*380907c9SMarouene Boubakri #include <kernel/misc.h> 11*380907c9SMarouene Boubakri #include <platform_config.h> 12*380907c9SMarouene Boubakri #include <types_ext.h> 13*380907c9SMarouene Boubakri 14*380907c9SMarouene Boubakri #ifdef CFG_RISCV_M_MODE 15*380907c9SMarouene Boubakri 16*380907c9SMarouene Boubakri /* Machine software-interrupt pending register for a specific hart */ 17*380907c9SMarouene Boubakri #define CLINT_MSIP(hart) (CLINT_BASE + (4 * (hart))) 18*380907c9SMarouene Boubakri /* Register for setting mtimecmp for a specific hart */ 19*380907c9SMarouene Boubakri #define CLINT_MTIMECMP(hart)(CLINT_BASE + 0x4000 + (8 * (hart))) 20*380907c9SMarouene Boubakri /* Number of cycles counted from the RTCCLK input */ 21*380907c9SMarouene Boubakri #define CLINT_MTIME (CLINT_BASE + 0xbff8) 22*380907c9SMarouene Boubakri clint_ipi_send(unsigned long hart)23*380907c9SMarouene Boubakristatic inline void clint_ipi_send(unsigned long hart) 24*380907c9SMarouene Boubakri { 25*380907c9SMarouene Boubakri assert(hart < CFG_TEE_CORE_NB_CORE); 26*380907c9SMarouene Boubakri io_write32(CLINT_MSIP(hart), 1); 27*380907c9SMarouene Boubakri } 28*380907c9SMarouene Boubakri clint_ipi_clear(unsigned long hart)29*380907c9SMarouene Boubakristatic inline void clint_ipi_clear(unsigned long hart) 30*380907c9SMarouene Boubakri { 31*380907c9SMarouene Boubakri assert(hart < CFG_TEE_CORE_NB_CORE); 32*380907c9SMarouene Boubakri io_write32(CLINT_MSIP(hart), 0); 33*380907c9SMarouene Boubakri } 34*380907c9SMarouene Boubakri clint_set_mtimecmp(uint64_t timecmp)35*380907c9SMarouene Boubakristatic inline void clint_set_mtimecmp(uint64_t timecmp) 36*380907c9SMarouene Boubakri { 37*380907c9SMarouene Boubakri /* Each hart has a separate source of timer interrupts */ 38*380907c9SMarouene Boubakri io_write64(CLINT_MTIMECMP(get_core_pos()), timecmp); 39*380907c9SMarouene Boubakri } 40*380907c9SMarouene Boubakri clint_get_mtimecmp(void)41*380907c9SMarouene Boubakristatic inline uint64_t clint_get_mtimecmp(void) 42*380907c9SMarouene Boubakri { 43*380907c9SMarouene Boubakri return io_read64(CLINT_MTIMECMP(get_core_pos())); 44*380907c9SMarouene Boubakri } 45*380907c9SMarouene Boubakri clint_get_mtime(void)46*380907c9SMarouene Boubakristatic inline uint64_t clint_get_mtime(void) 47*380907c9SMarouene Boubakri { 48*380907c9SMarouene Boubakri return io_read64(CLINT_MTIME); 49*380907c9SMarouene Boubakri } 50*380907c9SMarouene Boubakri clint_set_mtime(uint64_t mtime)51*380907c9SMarouene Boubakristatic inline void clint_set_mtime(uint64_t mtime) 52*380907c9SMarouene Boubakri { 53*380907c9SMarouene Boubakri io_write64(CLINT_MTIME, mtime); 54*380907c9SMarouene Boubakri } 55*380907c9SMarouene Boubakri 56*380907c9SMarouene Boubakri #endif /* CFG_RISCV_M_MODE */ 57*380907c9SMarouene Boubakri #endif /* __KERNEL_CLINT_H */ 58