1 /* 2 * Copyright (c) 2014, STMicroelectronics International N.V. 3 * Copyright (c) 2015, Linaro Limited 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <mm/core_mmu.h> 30 #include <mm/core_memprot.h> 31 #include <tee/cache.h> 32 33 /* 34 * tee_uta_cache_operation - dynamic cache clean/inval request from a TA 35 * It follows ARM recommendation: 36 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246d/Beicdhde.html 37 * Note that this implementation assumes dsb operations are part of 38 * cache_maintenance_l1(), and L2 cache sync are part of 39 * cache_maintenance_l2() 40 */ 41 TEE_Result cache_operation(enum utee_cache_operation op, void *va, size_t len) 42 { 43 TEE_Result res; 44 paddr_t pa; 45 46 pa = virt_to_phys(va); 47 if (!pa) 48 return TEE_ERROR_ACCESS_DENIED; 49 50 switch (op) { 51 case TEE_CACHEFLUSH: 52 #ifdef CFG_PL310 53 /* Clean L1, Flush L2, Flush L1 */ 54 res = cache_maintenance_l1(DCACHE_AREA_CLEAN, va, len); 55 if (res != TEE_SUCCESS) 56 return res; 57 res = cache_maintenance_l2(L2CACHE_AREA_CLEAN_INV, pa, len); 58 if (res != TEE_SUCCESS) 59 return res; 60 #endif 61 return cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, va, len); 62 63 case TEE_CACHECLEAN: 64 /* Clean L1, Clean L2 */ 65 res = cache_maintenance_l1(DCACHE_AREA_CLEAN, va, len); 66 if (res != TEE_SUCCESS) 67 return res; 68 return cache_maintenance_l2(L2CACHE_AREA_CLEAN, pa, len); 69 70 case TEE_CACHEINVALIDATE: 71 /* Inval L2, Inval L1 */ 72 res = cache_maintenance_l2(L2CACHE_AREA_INVALIDATE, pa, len); 73 if (res != TEE_SUCCESS) 74 return res; 75 return cache_maintenance_l1(DCACHE_AREA_INVALIDATE, va, len); 76 77 default: 78 return TEE_ERROR_NOT_SUPPORTED; 79 } 80 } 81