xref: /optee_os/core/arch/arm/sm/sm_a32.S (revision a1d5c81f8834a9d2c6f4372cce2e59e70e709121) 
1/* SPDX-License-Identifier: BSD-2-Clause */
2/*
3 * Copyright (c) 2016, Linaro Limited
4 * Copyright (c) 2014, STMicroelectronics International N.V.
5 */
6
7#include <arm32_macros.S>
8#include <arm.h>
9#include <asm.S>
10#include <generated/asm-defines.h>
11#include <keep.h>
12#include <sm/optee_smc.h>
13#include <sm/sm.h>
14#include <sm/teesmc_opteed.h>
15#include <sm/teesmc_opteed_macros.h>
16#include <util.h>
17
18#define SM_CTX_SEC_END	(SM_CTX_SEC + SM_CTX_SEC_SIZE)
19
20	.macro save_regs mode
21	cps	\mode
22	mrs	r2, spsr
23	str	r2, [r0], #4
24	str	sp, [r0], #4
25	str	lr, [r0], #4
26	.endm
27
28FUNC sm_save_unbanked_regs , :
29UNWIND(	.cantunwind)
30	/* User mode registers has to be saved from system mode */
31	cps	#CPSR_MODE_SYS
32	str	sp, [r0], #4
33	str	lr, [r0], #4
34
35	save_regs	#CPSR_MODE_IRQ
36	save_regs	#CPSR_MODE_FIQ
37	save_regs	#CPSR_MODE_SVC
38	save_regs	#CPSR_MODE_ABT
39	save_regs	#CPSR_MODE_UND
40
41#ifdef CFG_SM_NO_CYCLE_COUNTING
42	read_pmcr r2
43	stm	r0!, {r2}
44#endif
45
46#ifdef CFG_FTRACE_SUPPORT
47	read_cntkctl r2
48	stm	r0!, {r2}
49#endif
50	cps	#CPSR_MODE_MON
51	bx	lr
52END_FUNC sm_save_unbanked_regs
53
54	.macro restore_regs mode
55	cps	\mode
56	ldr	r2, [r0], #4
57	ldr	sp, [r0], #4
58	ldr	lr, [r0], #4
59	msr	spsr_fsxc, r2
60	.endm
61
62/* Restores the mode specific registers */
63FUNC sm_restore_unbanked_regs , :
64UNWIND(	.cantunwind)
65	/* User mode registers has to be saved from system mode */
66	cps	#CPSR_MODE_SYS
67	ldr	sp, [r0], #4
68	ldr	lr, [r0], #4
69
70	restore_regs	#CPSR_MODE_IRQ
71	restore_regs	#CPSR_MODE_FIQ
72	restore_regs	#CPSR_MODE_SVC
73	restore_regs	#CPSR_MODE_ABT
74	restore_regs	#CPSR_MODE_UND
75
76#ifdef CFG_SM_NO_CYCLE_COUNTING
77	ldm	r0!, {r2}
78	write_pmcr r2
79#endif
80
81#ifdef CFG_FTRACE_SUPPORT
82	ldm	r0!, {r2}
83	write_cntkctl r2
84#endif
85	cps	#CPSR_MODE_MON
86	bx	lr
87END_FUNC sm_restore_unbanked_regs
88
89/*
90 * stack_tmp is used as stack, the top of the stack is reserved to hold
91 * struct sm_ctx, everything below is for normal stack usage. As several
92 * different CPU modes are using the same stack it's important that switch
93 * of CPU mode isn't done until one mode is done. This means FIQ, IRQ and
94 * Async abort has to be masked while using stack_tmp.
95 */
96LOCAL_FUNC sm_smc_entry , :
97UNWIND(	.cantunwind)
98	srsdb	sp!, #CPSR_MODE_MON
99	push	{r0-r7}
100
101	clrex		/* Clear the exclusive monitor */
102
103	/* Find out if we're doing an secure or non-secure entry */
104	read_scr r1
105	tst	r1, #SCR_NS
106	bne	.smc_from_nsec
107
108	/*
109	 * As we're coming from secure world (NS bit cleared) the stack
110	 * pointer points to sm_ctx.sec.r0 at this stage. After the
111	 * instruction below the stack pointer points to sm_ctx.
112	 */
113	sub	sp, sp, #(SM_CTX_SEC + SM_SEC_CTX_R0)
114
115	/* Save secure context */
116	add	r0, sp, #SM_CTX_SEC
117	bl	sm_save_unbanked_regs
118
119	/*
120	 * On FIQ exit we're restoring the non-secure context unchanged, on
121	 * all other exits we're shifting r1-r4 from secure context into
122	 * r0-r3 in non-secure context.
123	 */
124	add	r8, sp, #(SM_CTX_SEC + SM_SEC_CTX_R0)
125	ldm	r8, {r0-r4}
126	mov_imm	r9, TEESMC_OPTEED_RETURN_FIQ_DONE
127	cmp	r0, r9
128	addne	r8, sp, #(SM_CTX_NSEC + SM_NSEC_CTX_R0)
129	stmne	r8, {r1-r4}
130
131	/* Restore non-secure context */
132	add	r0, sp, #SM_CTX_NSEC
133	bl	sm_restore_unbanked_regs
134
135.sm_ret_to_nsec:
136	/*
137	 * Return to non-secure world
138	 */
139	add     r0, sp, #(SM_CTX_NSEC + SM_NSEC_CTX_R8)
140	ldm	r0, {r8-r12}
141
142#ifdef CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME
143	/*
144	 * Prevent leaking information about which code has been executed.
145	 * This is required to be used together with
146	 * CFG_CORE_WORKAROUND_SPECTRE_BP to protect Cortex A15 CPUs too.
147	 *
148	 * CFG_CORE_WORKAROUND_SPECTRE_BP also invalidates the branch
149	 * predictor on affected CPUs. In the cases where an alternative
150	 * vector has been installed the branch predictor is already
151	 * invalidated so invalidating here again would be redundant, but
152	 * testing for that is more trouble than it's worth.
153	 */
154	write_bpiall
155#endif
156
157	/* Update SCR */
158	read_scr r0
159	orr	r0, r0, #(SCR_NS | SCR_FIQ) /* Set NS and FIQ bit in SCR */
160	write_scr r0
161	/*
162	 * isb not needed since we're doing an exception return below
163	 * without dependency to the changes in SCR before that.
164	 */
165
166	add	sp, sp, #(SM_CTX_NSEC + SM_NSEC_CTX_R0)
167	b	.sm_exit
168
169.smc_from_nsec:
170	/*
171	 * As we're coming from non-secure world (NS bit set) the stack
172	 * pointer points to sm_ctx.nsec.r0 at this stage. After the
173	 * instruction below the stack pointer points to sm_ctx.
174	 */
175	sub	sp, sp, #(SM_CTX_NSEC + SM_NSEC_CTX_R0)
176
177	bic	r1, r1, #(SCR_NS | SCR_FIQ) /* Clear NS and FIQ bit in SCR */
178	write_scr r1
179	isb
180
181	add	r0, sp, #(SM_CTX_NSEC + SM_NSEC_CTX_R8)
182	stm	r0, {r8-r12}
183
184	mov	r0, sp
185	bl	sm_from_nsec
186	cmp	r0, #SM_EXIT_TO_NON_SECURE
187	beq	.sm_ret_to_nsec
188
189	/*
190	 * Continue into secure world
191	 */
192	add	sp, sp, #(SM_CTX_SEC + SM_SEC_CTX_R0)
193
194.sm_exit:
195	pop	{r0-r7}
196	rfefd	sp!
197END_FUNC sm_smc_entry
198
199/*
200 * FIQ handling
201 *
202 * Saves CPU context in the same way as sm_smc_entry() above. The CPU
203 * context will later be restored by sm_smc_entry() when handling a return
204 * from FIQ.
205 */
206LOCAL_FUNC sm_fiq_entry , :
207UNWIND(	.cantunwind)
208	/* FIQ has a +4 offset for lr compared to preferred return address */
209	sub	lr, lr, #4
210	/* sp points just past struct sm_sec_ctx */
211	srsdb	sp!, #CPSR_MODE_MON
212	push	{r0-r7}
213
214	clrex		/* Clear the exclusive monitor */
215
216	/*
217	 * As we're coming from non-secure world the stack pointer points
218	 * to sm_ctx.nsec.r0 at this stage. After the instruction below the
219	 * stack pointer points to sm_ctx.
220	 */
221	sub	sp, sp, #(SM_CTX_NSEC + SM_NSEC_CTX_R0)
222
223	/* Update SCR */
224	read_scr r1
225	bic	r1, r1, #(SCR_NS | SCR_FIQ) /* Clear NS and FIQ bit in SCR */
226	write_scr r1
227	isb
228
229	/* Save non-secure context */
230	add	r0, sp, #SM_CTX_NSEC
231	bl	sm_save_unbanked_regs
232	add     r0, sp, #(SM_CTX_NSEC + SM_NSEC_CTX_R8)
233	stm	r0!, {r8-r12}
234
235	/* Set FIQ entry */
236	ldr	r0, =vector_fiq_entry
237	str	r0, [sp, #(SM_CTX_SEC + SM_SEC_CTX_MON_LR)]
238
239	/* Restore secure context */
240	add	r0, sp, #SM_CTX_SEC
241	bl	sm_restore_unbanked_regs
242
243	add	sp, sp, #(SM_CTX_SEC + SM_SEC_CTX_MON_LR)
244
245	rfefd	sp!
246END_FUNC sm_fiq_entry
247
248        .align	5
249LOCAL_FUNC sm_vect_table , :
250UNWIND(	.cantunwind)
251	b	.		/* Reset			*/
252	b	.		/* Undefined instruction	*/
253	b	sm_smc_entry	/* Secure monitor call		*/
254	b	.		/* Prefetch abort		*/
255	b	.		/* Data abort			*/
256	b	.		/* Reserved			*/
257	b	.		/* IRQ				*/
258	b	sm_fiq_entry	/* FIQ				*/
259
260#ifdef CFG_CORE_WORKAROUND_SPECTRE_BP
261	.macro vector_prologue_spectre
262		/*
263		 * This depends on SP being 8 byte aligned, that is, the
264		 * lowest three bits in SP are zero.
265		 *
266		 * The idea is to form a specific bit pattern in the lowest
267		 * three bits of SP depending on which entry in the vector
268		 * we enter via.  This is done by adding 1 to SP in each
269		 * entry but the last.
270		 */
271		add	sp, sp, #1	/* 7:111 Reset			*/
272		add	sp, sp, #1	/* 6:110 Undefined instruction	*/
273		add	sp, sp, #1	/* 5:101 Secure monitor call	*/
274		add	sp, sp, #1	/* 4:100 Prefetch abort		*/
275		add	sp, sp, #1	/* 3:011 Data abort		*/
276		add	sp, sp, #1	/* 2:010 Reserved		*/
277		add	sp, sp, #1	/* 1:001 IRQ			*/
278		nop			/* 0:000 FIQ			*/
279	.endm
280
281	.align 5
282sm_vect_table_a15:
283	vector_prologue_spectre
284	/*
285	 * Invalidate the branch predictor for the current processor.
286	 * For Cortex-A8 ACTLR[6] has to be set to 1 for BPIALL to be
287	 * effective.
288	 * Note that the BPIALL instruction is not effective in
289	 * invalidating the branch predictor on Cortex-A15. For that CPU,
290	 * set ACTLR[0] to 1 during early processor initialisation, and
291	 * invalidate the branch predictor by performing an ICIALLU
292	 * instruction. See also:
293	 * https://github.com/ARM-software/arm-trusted-firmware/wiki/Arm-Trusted-Firmware-Security-Advisory-TFV-6#variant-2-cve-2017-5715
294	 */
295	write_iciallu
296	isb
297	b	1f
298
299	.align 5
300sm_vect_table_bpiall:
301	vector_prologue_spectre
302	/* Invalidate the branch predictor for the current processor. */
303	write_bpiall
304	isb
305
3061:
307	/*
308	 * Only two exception does normally occur, smc and fiq. With all
309	 * other exceptions it's good enough to just spinn, the lowest bits
310	 * still tells which exception we're stuck with when attaching a
311	 * debugger.
312	 */
313
314	/* Test for FIQ, all the lowest bits of SP are supposed to be 0 */
315	tst	sp, #(BIT(0) | BIT(1) | BIT(2))
316	beq	sm_fiq_entry
317
318	/* Test for SMC, xor the lowest bits of SP to be 0 */
319	eor	sp, sp, #(BIT(0) | BIT(2))
320	tst	sp, #(BIT(0) | BIT(1) | BIT(2))
321	beq	sm_smc_entry
322
323	/* unhandled exception */
324	b	.
325#endif /*!CFG_CORE_WORKAROUND_SPECTRE_BP*/
326END_FUNC sm_vect_table
327
328/* void sm_init(vaddr_t stack_pointer); */
329FUNC sm_init , :
330	/* Set monitor stack */
331	mrs	r1, cpsr
332	cps	#CPSR_MODE_MON
333	/* Point just beyond sm_ctx.sec */
334	sub	sp, r0, #(SM_CTX_SIZE - SM_CTX_SEC_END)
335
336#ifdef CFG_INIT_CNTVOFF
337	read_scr r0
338	orr	r0, r0, #SCR_NS /* Set NS bit in SCR */
339	write_scr r0
340	isb
341
342	/*
343	 * Accessing CNTVOFF:
344	 * If the implementation includes the Virtualization Extensions
345	 * this is a RW register, accessible from Hyp mode, and
346	 * from Monitor mode when SCR.NS is set to 1.
347	 * If the implementation includes the Security Extensions
348	 * but not the Virtualization Extensions, an MCRR or MRRC to
349	 * the CNTVOFF encoding is UNPREDICTABLE if executed in Monitor
350	 * mode, regardless of the value of SCR.NS.
351	 */
352	read_id_pfr1 r2
353	mov	r3, r2
354	ands    r3, r3, #IDPFR1_GENTIMER_MASK
355	beq	.no_gentimer
356	ands    r2, r2, #IDPFR1_VIRT_MASK
357	beq	.no_gentimer
358	mov	r2, #0
359	write_cntvoff r2, r2
360
361.no_gentimer:
362	bic	r0, r0, #SCR_NS /* Clr NS bit in SCR */
363	write_scr r0
364	isb
365#endif
366#ifdef CFG_SM_NO_CYCLE_COUNTING
367	read_pmcr r0
368	orr	r0, #PMCR_DP
369	write_pmcr r0
370#endif
371	msr	cpsr, r1
372
373#ifdef CFG_CORE_WORKAROUND_SPECTRE_BP
374	/*
375	 * For unrecognized CPUs we fall back to the vector used for
376	 * unaffected CPUs. Cortex A-15 has special treatment compared to
377	 * the other affected Cortex CPUs.
378	 */
379	read_midr r1
380	ubfx	r2, r1, #MIDR_IMPLEMENTER_SHIFT, #MIDR_IMPLEMENTER_WIDTH
381	cmp	r2, #MIDR_IMPLEMENTER_ARM
382	bne	1f
383
384	ubfx	r2, r1, #MIDR_PRIMARY_PART_NUM_SHIFT, \
385			#MIDR_PRIMARY_PART_NUM_WIDTH
386
387	movw	r3, #CORTEX_A8_PART_NUM
388	cmp	r2, r3
389	movwne	r3, #CORTEX_A9_PART_NUM
390	cmpne	r2, r3
391	movwne	r3, #CORTEX_A17_PART_NUM
392	cmpne	r2, r3
393	ldreq	r0, =sm_vect_table_bpiall
394	beq	2f
395
396	movw	r3, #CORTEX_A15_PART_NUM
397	cmp	r2, r3
398	ldreq	r0, =sm_vect_table_a15
399	beq	2f
400#endif
401	/* Set monitor vector (MVBAR) */
4021:	ldr	r0, =sm_vect_table
4032:	write_mvbar r0
404
405	bx	lr
406END_FUNC sm_init
407DECLARE_KEEP_PAGER sm_init
408
409
410/* struct sm_nsec_ctx *sm_get_nsec_ctx(void); */
411FUNC sm_get_nsec_ctx , :
412	mrs	r1, cpsr
413	cps	#CPSR_MODE_MON
414	/*
415	 * As we're in secure mode mon_sp points just beyond sm_ctx.sec,
416	 * which allows us to calculate the address of sm_ctx.nsec.
417	 */
418	add	r0, sp, #(SM_CTX_NSEC - SM_CTX_SEC_END)
419	msr	cpsr, r1
420
421	bx	lr
422END_FUNC sm_get_nsec_ctx
423