1/* 2 * Copyright 2017 NXP 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#include <arm.h> 29#include <arm32_macros.S> 30#include <asm.S> 31#include <kernel/cache_helpers.h> 32#include <kernel/unwind.h> 33 34FUNC psci_disable_smp, : 35UNWIND( .fnstart) 36 read_actlr r0 37 bic r0, r0, #ACTLR_SMP 38 write_actlr r0 39 isb 40 bx lr 41UNWIND( .fnend) 42END_FUNC psci_disable_smp 43 44FUNC psci_enable_smp, : 45UNWIND( .fnstart) 46 read_actlr r0 47 orr r0, r0, #ACTLR_SMP 48 write_actlr r0 49 isb 50 bx lr 51UNWIND( .fnend) 52END_FUNC psci_enable_smp 53 54FUNC psci_armv7_cpu_off, : 55UNWIND( .fnstart) 56 push {r12, lr} 57UNWIND( .save {r12, lr}) 58 59 mov r0, #DCACHE_OP_CLEAN_INV 60 bl dcache_op_all 61 62 /* Disable Cache */ 63 read_sctlr r0 64 bic r0, r0, #SCTLR_C 65 write_sctlr r0 66 isb 67 dsb 68 69 mov r0, #DCACHE_OP_CLEAN_INV 70 bl dcache_op_all 71 72 clrex 73 74 bl psci_disable_smp 75 76 pop {r12, pc} 77UNWIND( .fnend) 78END_FUNC psci_armv7_cpu_off 79