1 /* 2 * Copyright (c) 2016, Xilinx Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <platform_config.h> 29 30 #include <stdint.h> 31 #include <string.h> 32 33 #include <drivers/gic.h> 34 #include <drivers/cdns_uart.h> 35 36 #include <arm.h> 37 #include <console.h> 38 #include <kernel/generic_boot.h> 39 #include <kernel/pm_stubs.h> 40 #include <kernel/misc.h> 41 #include <kernel/tee_time.h> 42 #include <mm/core_memprot.h> 43 #include <tee/entry_fast.h> 44 #include <tee/entry_std.h> 45 #include <trace.h> 46 47 static void main_fiq(void); 48 static struct gic_data gic_data; 49 50 static const struct thread_handlers handlers = { 51 .std_smc = tee_entry_std, 52 .fast_smc = tee_entry_fast, 53 .fiq = main_fiq, 54 #if defined(CFG_WITH_ARM_TRUSTED_FW) 55 .cpu_on = cpu_on_handler, 56 .cpu_off = pm_do_nothing, 57 .cpu_suspend = pm_do_nothing, 58 .cpu_resume = pm_do_nothing, 59 .system_off = pm_do_nothing, 60 .system_reset = pm_do_nothing, 61 #else 62 .cpu_on = pm_panic, 63 .cpu_off = pm_panic, 64 .cpu_suspend = pm_panic, 65 .cpu_resume = pm_panic, 66 .system_off = pm_panic, 67 .system_reset = pm_panic, 68 #endif 69 }; 70 71 const struct thread_handlers *generic_boot_get_handlers(void) 72 { 73 return &handlers; 74 } 75 76 void main_init_gic(void) 77 { 78 vaddr_t gicc_base, gicd_base; 79 80 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 81 MEM_AREA_IO_SEC); 82 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 83 MEM_AREA_IO_SEC); 84 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 85 gic_init_base_addr(&gic_data, gicc_base, gicd_base); 86 } 87 88 static void main_fiq(void) 89 { 90 gic_it_handle(&gic_data); 91 } 92 93 static vaddr_t console_base(void) 94 { 95 static void *va; 96 97 if (cpu_mmu_enabled()) { 98 if (!va) 99 va = phys_to_virt(CONSOLE_UART_BASE, MEM_AREA_IO_SEC); 100 return (vaddr_t)va; 101 } 102 103 return CONSOLE_UART_BASE; 104 } 105 106 void console_init(void) 107 { 108 cdns_uart_init(console_base(), CONSOLE_UART_CLK_IN_HZ, 109 CONSOLE_BAUDRATE); 110 } 111 112 void console_putc(int ch) 113 { 114 if (ch == '\n') 115 cdns_uart_putc('\r', console_base()); 116 cdns_uart_putc(ch, console_base()); 117 } 118 119 void console_flush(void) 120 { 121 cdns_uart_flush(console_base()); 122 } 123