1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016, Xilinx Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <platform_config.h> 30 31 #include <stdint.h> 32 #include <string.h> 33 34 #include <drivers/gic.h> 35 #include <drivers/cdns_uart.h> 36 #include <drivers/zynqmp_csu.h> 37 38 #include <arm.h> 39 #include <console.h> 40 #include <io.h> 41 #include <kernel/boot.h> 42 #include <kernel/interrupt.h> 43 #include <kernel/misc.h> 44 #include <kernel/tee_common_otp.h> 45 #include <kernel/tee_time.h> 46 #include <mm/core_memprot.h> 47 #include <tee/tee_fs.h> 48 #include <trace.h> 49 50 static struct gic_data gic_data __nex_bss; 51 static struct cdns_uart_data console_data __nex_bss; 52 53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 54 ROUNDDOWN(CONSOLE_UART_BASE, CORE_MMU_PGDIR_SIZE), 55 CORE_MMU_PGDIR_SIZE); 56 57 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 58 ROUNDDOWN(GIC_BASE, CORE_MMU_PGDIR_SIZE), 59 CORE_MMU_PGDIR_SIZE); 60 61 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 62 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE), 63 CORE_MMU_PGDIR_SIZE); 64 #if defined(CFG_ZYNQMP_CSU) 65 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CSU_BASE, CSU_SIZE); 66 #endif 67 68 #if CFG_DDR_SIZE > 0x80000000 69 70 #ifdef CFG_ARM32_core 71 #error DDR size over 2 GiB is not supported in 32 bit ARM mode 72 #endif 73 74 register_ddr(DRAM0_BASE, 0x80000000); 75 register_ddr(DRAM1_BASE, CFG_DDR_SIZE - 0x80000000); 76 #else 77 register_ddr(DRAM0_BASE, CFG_DDR_SIZE); 78 #endif 79 80 void main_init_gic(void) 81 { 82 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 83 gic_init_base_addr(&gic_data, GIC_BASE + GICC_OFFSET, 84 GIC_BASE + GICD_OFFSET); 85 } 86 87 void itr_core_handler(void) 88 { 89 gic_it_handle(&gic_data); 90 } 91 92 void console_init(void) 93 { 94 cdns_uart_init(&console_data, CONSOLE_UART_BASE, 95 CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE); 96 register_serial_console(&console_data.chip); 97 } 98 99 #if defined(CFG_RPMB_FS) 100 bool plat_rpmb_key_is_ready(void) 101 { 102 vaddr_t csu = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, CSU_SIZE); 103 struct tee_hw_unique_key hwkey = { }; 104 uint32_t status = 0; 105 106 if (tee_otp_get_hw_unique_key(&hwkey)) 107 return false; 108 109 /* 110 * For security reasons, we don't allow writing the RPMB key using the 111 * development HUK even though it is unique. 112 */ 113 status = io_read32(csu + ZYNQMP_CSU_STATUS_OFFSET); 114 if (status & ZYNQMP_CSU_STATUS_AUTH) 115 return true; 116 117 return false; 118 } 119 #endif 120