1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * All rights reserved. 5 * Copyright (c) 2016, Wind River Systems. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arm32.h> 32 #include <console.h> 33 #include <drivers/cdns_uart.h> 34 #include <drivers/gic.h> 35 #include <io.h> 36 #include <kernel/generic_boot.h> 37 #include <kernel/misc.h> 38 #include <kernel/panic.h> 39 #include <kernel/pm_stubs.h> 40 #include <kernel/tz_ssvce_pl310.h> 41 #include <mm/core_mmu.h> 42 #include <mm/core_memprot.h> 43 #include <platform_config.h> 44 #include <platform_smc.h> 45 #include <stdint.h> 46 #include <tee/entry_fast.h> 47 #include <tee/entry_std.h> 48 49 static const struct thread_handlers handlers = { 50 .cpu_on = pm_panic, 51 .cpu_off = pm_panic, 52 .cpu_suspend = pm_panic, 53 .cpu_resume = pm_panic, 54 .system_off = pm_panic, 55 .system_reset = pm_panic, 56 }; 57 58 static struct gic_data gic_data; 59 static struct cdns_uart_data console_data; 60 61 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 62 CORE_MMU_PGDIR_SIZE); 63 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 64 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_PGDIR_SIZE); 65 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SLCR_BASE, CORE_MMU_PGDIR_SIZE); 66 67 const struct thread_handlers *generic_boot_get_handlers(void) 68 { 69 return &handlers; 70 } 71 72 void plat_cpu_reset_late(void) 73 { 74 if (!get_core_pos()) { 75 /* primary core */ 76 #if defined(CFG_BOOT_SECONDARY_REQUEST) 77 /* set secondary entry address and release core */ 78 io_write32(SECONDARY_ENTRY_DROP, TEE_LOAD_ADDR); 79 dsb(); 80 sev(); 81 #endif 82 83 /* SCU config */ 84 io_write32(SCU_BASE + SCU_INV_SEC, SCU_INV_CTRL_INIT); 85 io_write32(SCU_BASE + SCU_SAC, SCU_SAC_CTRL_INIT); 86 io_write32(SCU_BASE + SCU_NSAC, SCU_NSAC_CTRL_INIT); 87 88 /* SCU enable */ 89 io_setbits32(SCU_BASE + SCU_CTRL, 0x1); 90 91 /* NS Access control */ 92 io_write32(SECURITY2_SDIO0, ACCESS_BITS_ALL); 93 io_write32(SECURITY3_SDIO1, ACCESS_BITS_ALL); 94 io_write32(SECURITY4_QSPI, ACCESS_BITS_ALL); 95 io_write32(SECURITY6_APB_SLAVES, ACCESS_BITS_ALL); 96 97 io_write32(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK); 98 99 io_write32(SLCR_TZ_DDR_RAM, ACCESS_BITS_ALL); 100 io_write32(SLCR_TZ_DMA_NS, ACCESS_BITS_ALL); 101 io_write32(SLCR_TZ_DMA_IRQ_NS, ACCESS_BITS_ALL); 102 io_write32(SLCR_TZ_DMA_PERIPH_NS, ACCESS_BITS_ALL); 103 io_write32(SLCR_TZ_GEM, ACCESS_BITS_ALL); 104 io_write32(SLCR_TZ_SDIO, ACCESS_BITS_ALL); 105 io_write32(SLCR_TZ_USB, ACCESS_BITS_ALL); 106 107 io_write32(SLCR_LOCK, SLCR_LOCK_MAGIC); 108 } 109 } 110 111 void console_init(void) 112 { 113 cdns_uart_init(&console_data, CONSOLE_UART_BASE, 0, 0); 114 register_serial_console(&console_data.chip); 115 } 116 117 vaddr_t pl310_base(void) 118 { 119 static void *va; 120 121 if (cpu_mmu_enabled()) { 122 if (!va) 123 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 124 return (vaddr_t)va; 125 } 126 return PL310_BASE; 127 } 128 129 void arm_cl2_config(vaddr_t pl310_base) 130 { 131 /* Disable PL310 */ 132 io_write32(pl310_base + PL310_CTRL, 0); 133 134 /* 135 * Xilinx AR#54190 recommends setting L2C RAM in SLCR 136 * to 0x00020202 for proper cache operations. 137 */ 138 io_write32(SLCR_L2C_RAM, SLCR_L2C_RAM_VALUE); 139 140 io_write32(pl310_base + PL310_TAG_RAM_CTRL, PL310_TAG_RAM_CTRL_INIT); 141 io_write32(pl310_base + PL310_DATA_RAM_CTRL, PL310_DATA_RAM_CTRL_INIT); 142 io_write32(pl310_base + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); 143 io_write32(pl310_base + PL310_PREFETCH_CTRL, PL310_PREFETCH_CTRL_INIT); 144 io_write32(pl310_base + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); 145 146 /* invalidate all cache ways */ 147 arm_cl2_invbyway(pl310_base); 148 } 149 150 void arm_cl2_enable(vaddr_t pl310_base) 151 { 152 uint32_t val; 153 154 /* Enable PL310 ctrl -> only set lsb bit */ 155 io_write32(pl310_base + PL310_CTRL, 1); 156 157 /* if L2 FLZW enable, enable in L1 */ 158 val = io_read32(pl310_base + PL310_AUX_CTRL); 159 if (val & 1) 160 write_actlr(read_actlr() | (1 << 3)); 161 } 162 163 void main_init_gic(void) 164 { 165 vaddr_t gicc_base; 166 vaddr_t gicd_base; 167 168 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 169 MEM_AREA_IO_SEC); 170 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 171 MEM_AREA_IO_SEC); 172 173 if (!gicc_base || !gicd_base) 174 panic(); 175 176 /* Initialize GIC */ 177 gic_init(&gic_data, gicc_base, gicd_base); 178 itr_init(&gic_data.chip); 179 } 180 181 void main_secondary_init_gic(void) 182 { 183 gic_cpu_init(&gic_data); 184 } 185 186 static vaddr_t slcr_access_range[] = { 187 0x004, 0x008, /* lock, unlock */ 188 0x100, 0x1FF, /* PLL */ 189 0x200, 0x2FF, /* Reset */ 190 0xA00, 0xAFF /* L2C */ 191 }; 192 193 static uint32_t write_slcr(uint32_t addr, uint32_t val) 194 { 195 uint32_t i; 196 197 for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { 198 if (addr >= slcr_access_range[i] && 199 addr <= slcr_access_range[i+1]) { 200 static vaddr_t va; 201 202 if (!va) 203 va = (vaddr_t)phys_to_virt(SLCR_BASE, 204 MEM_AREA_IO_SEC); 205 io_write32(va + addr, val); 206 return OPTEE_SMC_RETURN_OK; 207 } 208 } 209 return OPTEE_SMC_RETURN_EBADADDR; 210 } 211 212 static uint32_t read_slcr(uint32_t addr, uint32_t *val) 213 { 214 uint32_t i; 215 216 for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { 217 if (addr >= slcr_access_range[i] && 218 addr <= slcr_access_range[i+1]) { 219 static vaddr_t va; 220 221 if (!va) 222 va = (vaddr_t)phys_to_virt(SLCR_BASE, 223 MEM_AREA_IO_SEC); 224 *val = io_read32(va + addr); 225 return OPTEE_SMC_RETURN_OK; 226 } 227 } 228 return OPTEE_SMC_RETURN_EBADADDR; 229 } 230 231 /* Overriding the default __weak tee_entry_fast() */ 232 void tee_entry_fast(struct thread_smc_args *args) 233 { 234 switch (args->a0) { 235 case ZYNQ7K_SMC_SLCR_WRITE: 236 args->a0 = write_slcr(args->a1, args->a2); 237 break; 238 case ZYNQ7K_SMC_SLCR_READ: 239 args->a0 = read_slcr(args->a1, &args->a2); 240 break; 241 default: 242 __tee_entry_fast(args); 243 break; 244 } 245 } 246