1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * All rights reserved. 5 * Copyright (c) 2016, Wind River Systems. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arm32.h> 32 #include <console.h> 33 #include <drivers/cdns_uart.h> 34 #include <drivers/gic.h> 35 #include <io.h> 36 #include <kernel/boot.h> 37 #include <kernel/misc.h> 38 #include <kernel/panic.h> 39 #include <kernel/tz_ssvce_pl310.h> 40 #include <mm/core_mmu.h> 41 #include <mm/core_memprot.h> 42 #include <platform_config.h> 43 #include <platform_smc.h> 44 #include <stdint.h> 45 #include <tee/entry_fast.h> 46 47 static struct cdns_uart_data console_data; 48 49 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 50 CORE_MMU_PGDIR_SIZE); 51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_PGDIR_SIZE); 53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SLCR_BASE, CORE_MMU_PGDIR_SIZE); 54 55 void plat_primary_init_early(void) 56 { 57 /* primary core */ 58 #if defined(CFG_BOOT_SECONDARY_REQUEST) 59 /* set secondary entry address and release core */ 60 io_write32(SECONDARY_ENTRY_DROP, TEE_LOAD_ADDR); 61 dsb(); 62 sev(); 63 #endif 64 65 /* SCU config */ 66 io_write32(SCU_BASE + SCU_INV_SEC, SCU_INV_CTRL_INIT); 67 io_write32(SCU_BASE + SCU_SAC, SCU_SAC_CTRL_INIT); 68 io_write32(SCU_BASE + SCU_NSAC, SCU_NSAC_CTRL_INIT); 69 70 /* SCU enable */ 71 io_setbits32(SCU_BASE + SCU_CTRL, 0x1); 72 73 /* NS Access control */ 74 io_write32(SECURITY2_SDIO0, ACCESS_BITS_ALL); 75 io_write32(SECURITY3_SDIO1, ACCESS_BITS_ALL); 76 io_write32(SECURITY4_QSPI, ACCESS_BITS_ALL); 77 io_write32(SECURITY6_APB_SLAVES, ACCESS_BITS_ALL); 78 79 io_write32(SLCR_UNLOCK, SLCR_UNLOCK_MAGIC); 80 81 io_write32(SLCR_TZ_DDR_RAM, ACCESS_BITS_ALL); 82 io_write32(SLCR_TZ_DMA_NS, ACCESS_BITS_ALL); 83 io_write32(SLCR_TZ_DMA_IRQ_NS, ACCESS_BITS_ALL); 84 io_write32(SLCR_TZ_DMA_PERIPH_NS, ACCESS_BITS_ALL); 85 io_write32(SLCR_TZ_GEM, ACCESS_BITS_ALL); 86 io_write32(SLCR_TZ_SDIO, ACCESS_BITS_ALL); 87 io_write32(SLCR_TZ_USB, ACCESS_BITS_ALL); 88 89 io_write32(SLCR_LOCK, SLCR_LOCK_MAGIC); 90 } 91 92 void console_init(void) 93 { 94 cdns_uart_init(&console_data, CONSOLE_UART_BASE, 0, 0); 95 register_serial_console(&console_data.chip); 96 } 97 98 vaddr_t pl310_base(void) 99 { 100 static void *va; 101 102 if (cpu_mmu_enabled()) { 103 if (!va) 104 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC, 1); 105 return (vaddr_t)va; 106 } 107 return PL310_BASE; 108 } 109 110 void arm_cl2_config(vaddr_t pl310_base) 111 { 112 /* Disable PL310 */ 113 io_write32(pl310_base + PL310_CTRL, 0); 114 115 /* 116 * Xilinx AR#54190 recommends setting L2C RAM in SLCR 117 * to 0x00020202 for proper cache operations. 118 */ 119 io_write32(SLCR_L2C_RAM, SLCR_L2C_RAM_VALUE); 120 121 io_write32(pl310_base + PL310_TAG_RAM_CTRL, PL310_TAG_RAM_CTRL_INIT); 122 io_write32(pl310_base + PL310_DATA_RAM_CTRL, PL310_DATA_RAM_CTRL_INIT); 123 io_write32(pl310_base + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); 124 io_write32(pl310_base + PL310_PREFETCH_CTRL, PL310_PREFETCH_CTRL_INIT); 125 io_write32(pl310_base + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); 126 127 /* invalidate all cache ways */ 128 arm_cl2_invbyway(pl310_base); 129 } 130 131 void arm_cl2_enable(vaddr_t pl310_base) 132 { 133 uint32_t val; 134 135 /* Enable PL310 ctrl -> only set lsb bit */ 136 io_write32(pl310_base + PL310_CTRL, 1); 137 138 /* if L2 FLZW enable, enable in L1 */ 139 val = io_read32(pl310_base + PL310_AUX_CTRL); 140 if (val & 1) 141 write_actlr(read_actlr() | (1 << 3)); 142 } 143 144 void main_init_gic(void) 145 { 146 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 147 } 148 149 void main_secondary_init_gic(void) 150 { 151 gic_cpu_init(); 152 } 153 154 static vaddr_t slcr_access_range[] = { 155 0x004, 0x008, /* lock, unlock */ 156 0x100, 0x1FF, /* PLL */ 157 0x200, 0x2FF, /* Reset */ 158 0xA00, 0xAFF /* L2C */ 159 }; 160 161 static uint32_t write_slcr(uint32_t addr, uint32_t val) 162 { 163 uint32_t i; 164 165 for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { 166 if (addr >= slcr_access_range[i] && 167 addr <= slcr_access_range[i+1]) { 168 static vaddr_t va; 169 170 if (!va) 171 va = (vaddr_t)phys_to_virt(SLCR_BASE, 172 MEM_AREA_IO_SEC, 173 addr + 174 sizeof(uint32_t)); 175 io_write32(va + addr, val); 176 return OPTEE_SMC_RETURN_OK; 177 } 178 } 179 return OPTEE_SMC_RETURN_EBADADDR; 180 } 181 182 static uint32_t read_slcr(uint32_t addr, uint32_t *val) 183 { 184 uint32_t i; 185 186 for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { 187 if (addr >= slcr_access_range[i] && 188 addr <= slcr_access_range[i+1]) { 189 static vaddr_t va; 190 191 if (!va) 192 va = (vaddr_t)phys_to_virt(SLCR_BASE, 193 MEM_AREA_IO_SEC, 194 addr + 195 sizeof(uint32_t)); 196 *val = io_read32(va + addr); 197 return OPTEE_SMC_RETURN_OK; 198 } 199 } 200 return OPTEE_SMC_RETURN_EBADADDR; 201 } 202 203 /* Overriding the default __weak tee_entry_fast() */ 204 void tee_entry_fast(struct thread_smc_args *args) 205 { 206 switch (args->a0) { 207 case ZYNQ7K_SMC_SLCR_WRITE: 208 args->a0 = write_slcr(args->a1, args->a2); 209 break; 210 case ZYNQ7K_SMC_SLCR_READ: 211 args->a0 = read_slcr(args->a1, &args->a2); 212 break; 213 default: 214 __tee_entry_fast(args); 215 break; 216 } 217 } 218