1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * All rights reserved. 5 * Copyright (c) 2016, Wind River Systems. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arm32.h> 32 #include <console.h> 33 #include <drivers/cdns_uart.h> 34 #include <drivers/gic.h> 35 #include <io.h> 36 #include <kernel/generic_boot.h> 37 #include <kernel/misc.h> 38 #include <kernel/panic.h> 39 #include <kernel/pm_stubs.h> 40 #include <kernel/tz_ssvce_pl310.h> 41 #include <mm/core_mmu.h> 42 #include <mm/core_memprot.h> 43 #include <platform_config.h> 44 #include <platform_smc.h> 45 #include <stdint.h> 46 #include <tee/entry_fast.h> 47 #include <tee/entry_std.h> 48 49 static void main_fiq(void); 50 static void platform_tee_entry_fast(struct thread_smc_args *args); 51 52 static const struct thread_handlers handlers = { 53 .std_smc = tee_entry_std, 54 .fast_smc = platform_tee_entry_fast, 55 .nintr = main_fiq, 56 .cpu_on = pm_panic, 57 .cpu_off = pm_panic, 58 .cpu_suspend = pm_panic, 59 .cpu_resume = pm_panic, 60 .system_off = pm_panic, 61 .system_reset = pm_panic, 62 }; 63 64 static struct gic_data gic_data; 65 static struct cdns_uart_data console_data; 66 67 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CORE_MMU_DEVICE_SIZE); 68 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE); 69 register_phys_mem(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_DEVICE_SIZE); 70 register_phys_mem(MEM_AREA_IO_SEC, SLCR_BASE, CORE_MMU_DEVICE_SIZE); 71 72 const struct thread_handlers *generic_boot_get_handlers(void) 73 { 74 return &handlers; 75 } 76 77 static void main_fiq(void) 78 { 79 panic(); 80 } 81 82 void plat_cpu_reset_late(void) 83 { 84 if (!get_core_pos()) { 85 /* primary core */ 86 #if defined(CFG_BOOT_SECONDARY_REQUEST) 87 /* set secondary entry address and release core */ 88 write32(TEE_LOAD_ADDR, SECONDARY_ENTRY_DROP); 89 dsb(); 90 sev(); 91 #endif 92 93 /* SCU config */ 94 write32(SCU_INV_CTRL_INIT, SCU_BASE + SCU_INV_SEC); 95 write32(SCU_SAC_CTRL_INIT, SCU_BASE + SCU_SAC); 96 write32(SCU_NSAC_CTRL_INIT, SCU_BASE + SCU_NSAC); 97 98 /* SCU enable */ 99 write32(read32(SCU_BASE + SCU_CTRL) | 0x1, 100 SCU_BASE + SCU_CTRL); 101 102 /* NS Access control */ 103 write32(ACCESS_BITS_ALL, SECURITY2_SDIO0); 104 write32(ACCESS_BITS_ALL, SECURITY3_SDIO1); 105 write32(ACCESS_BITS_ALL, SECURITY4_QSPI); 106 write32(ACCESS_BITS_ALL, SECURITY6_APB_SLAVES); 107 108 write32(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK); 109 110 write32(ACCESS_BITS_ALL, SLCR_TZ_DDR_RAM); 111 write32(ACCESS_BITS_ALL, SLCR_TZ_DMA_NS); 112 write32(ACCESS_BITS_ALL, SLCR_TZ_DMA_IRQ_NS); 113 write32(ACCESS_BITS_ALL, SLCR_TZ_DMA_PERIPH_NS); 114 write32(ACCESS_BITS_ALL, SLCR_TZ_GEM); 115 write32(ACCESS_BITS_ALL, SLCR_TZ_SDIO); 116 write32(ACCESS_BITS_ALL, SLCR_TZ_USB); 117 118 write32(SLCR_LOCK_MAGIC, SLCR_LOCK); 119 } 120 } 121 122 void console_init(void) 123 { 124 cdns_uart_init(&console_data, CONSOLE_UART_BASE, 0, 0); 125 register_serial_console(&console_data.chip); 126 } 127 128 vaddr_t pl310_base(void) 129 { 130 static void *va; 131 132 if (cpu_mmu_enabled()) { 133 if (!va) 134 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 135 return (vaddr_t)va; 136 } 137 return PL310_BASE; 138 } 139 140 void arm_cl2_config(vaddr_t pl310_base) 141 { 142 /* Disable PL310 */ 143 write32(0, pl310_base + PL310_CTRL); 144 145 /* 146 * Xilinx AR#54190 recommends setting L2C RAM in SLCR 147 * to 0x00020202 for proper cache operations. 148 */ 149 write32(SLCR_L2C_RAM_VALUE, SLCR_L2C_RAM); 150 151 write32(PL310_TAG_RAM_CTRL_INIT, pl310_base + PL310_TAG_RAM_CTRL); 152 write32(PL310_DATA_RAM_CTRL_INIT, pl310_base + PL310_DATA_RAM_CTRL); 153 write32(PL310_AUX_CTRL_INIT, pl310_base + PL310_AUX_CTRL); 154 write32(PL310_PREFETCH_CTRL_INIT, pl310_base + PL310_PREFETCH_CTRL); 155 write32(PL310_POWER_CTRL_INIT, pl310_base + PL310_POWER_CTRL); 156 157 /* invalidate all cache ways */ 158 arm_cl2_invbyway(pl310_base); 159 } 160 161 void arm_cl2_enable(vaddr_t pl310_base) 162 { 163 uint32_t val; 164 165 /* Enable PL310 ctrl -> only set lsb bit */ 166 write32(1, pl310_base + PL310_CTRL); 167 168 /* if L2 FLZW enable, enable in L1 */ 169 val = read32(pl310_base + PL310_AUX_CTRL); 170 if (val & 1) 171 write_actlr(read_actlr() | (1 << 3)); 172 } 173 174 void main_init_gic(void) 175 { 176 vaddr_t gicc_base; 177 vaddr_t gicd_base; 178 179 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 180 MEM_AREA_IO_SEC); 181 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 182 MEM_AREA_IO_SEC); 183 184 if (!gicc_base || !gicd_base) 185 panic(); 186 187 /* Initialize GIC */ 188 gic_init(&gic_data, gicc_base, gicd_base); 189 itr_init(&gic_data.chip); 190 } 191 192 void main_secondary_init_gic(void) 193 { 194 gic_cpu_init(&gic_data); 195 } 196 197 static vaddr_t slcr_access_range[] = { 198 0x004, 0x008, /* lock, unlock */ 199 0x100, 0x1FF, /* PLL */ 200 0x200, 0x2FF, /* Reset */ 201 0xA00, 0xAFF /* L2C */ 202 }; 203 204 static uint32_t write_slcr(uint32_t addr, uint32_t val) 205 { 206 uint32_t i; 207 208 for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { 209 if (addr >= slcr_access_range[i] && 210 addr <= slcr_access_range[i+1]) { 211 static vaddr_t va; 212 213 if (!va) 214 va = (vaddr_t)phys_to_virt(SLCR_BASE, 215 MEM_AREA_IO_SEC); 216 write32(val, va + addr); 217 return OPTEE_SMC_RETURN_OK; 218 } 219 } 220 return OPTEE_SMC_RETURN_EBADADDR; 221 } 222 223 static uint32_t read_slcr(uint32_t addr, uint32_t *val) 224 { 225 uint32_t i; 226 227 for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { 228 if (addr >= slcr_access_range[i] && 229 addr <= slcr_access_range[i+1]) { 230 static vaddr_t va; 231 232 if (!va) 233 va = (vaddr_t)phys_to_virt(SLCR_BASE, 234 MEM_AREA_IO_SEC); 235 *val = read32(va + addr); 236 return OPTEE_SMC_RETURN_OK; 237 } 238 } 239 return OPTEE_SMC_RETURN_EBADADDR; 240 } 241 242 static void platform_tee_entry_fast(struct thread_smc_args *args) 243 { 244 switch (args->a0) { 245 case ZYNQ7K_SMC_SLCR_WRITE: 246 args->a0 = write_slcr(args->a1, args->a2); 247 break; 248 case ZYNQ7K_SMC_SLCR_READ: 249 args->a0 = read_slcr(args->a1, &args->a2); 250 break; 251 default: 252 tee_entry_fast(args); 253 break; 254 } 255 } 256