1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * All rights reserved. 5 * Copyright (c) 2016, Wind River Systems. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arm32.h> 32 #include <console.h> 33 #include <drivers/cdns_uart.h> 34 #include <drivers/gic.h> 35 #include <io.h> 36 #include <kernel/boot.h> 37 #include <kernel/misc.h> 38 #include <kernel/panic.h> 39 #include <kernel/tz_ssvce_pl310.h> 40 #include <mm/core_mmu.h> 41 #include <mm/core_memprot.h> 42 #include <platform_config.h> 43 #include <platform_smc.h> 44 #include <stdint.h> 45 #include <tee/entry_fast.h> 46 47 static struct gic_data gic_data; 48 static struct cdns_uart_data console_data; 49 50 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 51 CORE_MMU_PGDIR_SIZE); 52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_PGDIR_SIZE); 54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SLCR_BASE, CORE_MMU_PGDIR_SIZE); 55 56 void plat_primary_init_early(void) 57 { 58 /* primary core */ 59 #if defined(CFG_BOOT_SECONDARY_REQUEST) 60 /* set secondary entry address and release core */ 61 io_write32(SECONDARY_ENTRY_DROP, TEE_LOAD_ADDR); 62 dsb(); 63 sev(); 64 #endif 65 66 /* SCU config */ 67 io_write32(SCU_BASE + SCU_INV_SEC, SCU_INV_CTRL_INIT); 68 io_write32(SCU_BASE + SCU_SAC, SCU_SAC_CTRL_INIT); 69 io_write32(SCU_BASE + SCU_NSAC, SCU_NSAC_CTRL_INIT); 70 71 /* SCU enable */ 72 io_setbits32(SCU_BASE + SCU_CTRL, 0x1); 73 74 /* NS Access control */ 75 io_write32(SECURITY2_SDIO0, ACCESS_BITS_ALL); 76 io_write32(SECURITY3_SDIO1, ACCESS_BITS_ALL); 77 io_write32(SECURITY4_QSPI, ACCESS_BITS_ALL); 78 io_write32(SECURITY6_APB_SLAVES, ACCESS_BITS_ALL); 79 80 io_write32(SLCR_UNLOCK, SLCR_UNLOCK_MAGIC); 81 82 io_write32(SLCR_TZ_DDR_RAM, ACCESS_BITS_ALL); 83 io_write32(SLCR_TZ_DMA_NS, ACCESS_BITS_ALL); 84 io_write32(SLCR_TZ_DMA_IRQ_NS, ACCESS_BITS_ALL); 85 io_write32(SLCR_TZ_DMA_PERIPH_NS, ACCESS_BITS_ALL); 86 io_write32(SLCR_TZ_GEM, ACCESS_BITS_ALL); 87 io_write32(SLCR_TZ_SDIO, ACCESS_BITS_ALL); 88 io_write32(SLCR_TZ_USB, ACCESS_BITS_ALL); 89 90 io_write32(SLCR_LOCK, SLCR_LOCK_MAGIC); 91 } 92 93 void console_init(void) 94 { 95 cdns_uart_init(&console_data, CONSOLE_UART_BASE, 0, 0); 96 register_serial_console(&console_data.chip); 97 } 98 99 vaddr_t pl310_base(void) 100 { 101 static void *va; 102 103 if (cpu_mmu_enabled()) { 104 if (!va) 105 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC, 1); 106 return (vaddr_t)va; 107 } 108 return PL310_BASE; 109 } 110 111 void arm_cl2_config(vaddr_t pl310_base) 112 { 113 /* Disable PL310 */ 114 io_write32(pl310_base + PL310_CTRL, 0); 115 116 /* 117 * Xilinx AR#54190 recommends setting L2C RAM in SLCR 118 * to 0x00020202 for proper cache operations. 119 */ 120 io_write32(SLCR_L2C_RAM, SLCR_L2C_RAM_VALUE); 121 122 io_write32(pl310_base + PL310_TAG_RAM_CTRL, PL310_TAG_RAM_CTRL_INIT); 123 io_write32(pl310_base + PL310_DATA_RAM_CTRL, PL310_DATA_RAM_CTRL_INIT); 124 io_write32(pl310_base + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); 125 io_write32(pl310_base + PL310_PREFETCH_CTRL, PL310_PREFETCH_CTRL_INIT); 126 io_write32(pl310_base + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); 127 128 /* invalidate all cache ways */ 129 arm_cl2_invbyway(pl310_base); 130 } 131 132 void arm_cl2_enable(vaddr_t pl310_base) 133 { 134 uint32_t val; 135 136 /* Enable PL310 ctrl -> only set lsb bit */ 137 io_write32(pl310_base + PL310_CTRL, 1); 138 139 /* if L2 FLZW enable, enable in L1 */ 140 val = io_read32(pl310_base + PL310_AUX_CTRL); 141 if (val & 1) 142 write_actlr(read_actlr() | (1 << 3)); 143 } 144 145 void main_init_gic(void) 146 { 147 gic_init(&gic_data, GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 148 itr_init(&gic_data.chip); 149 } 150 151 void main_secondary_init_gic(void) 152 { 153 gic_cpu_init(&gic_data); 154 } 155 156 static vaddr_t slcr_access_range[] = { 157 0x004, 0x008, /* lock, unlock */ 158 0x100, 0x1FF, /* PLL */ 159 0x200, 0x2FF, /* Reset */ 160 0xA00, 0xAFF /* L2C */ 161 }; 162 163 static uint32_t write_slcr(uint32_t addr, uint32_t val) 164 { 165 uint32_t i; 166 167 for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { 168 if (addr >= slcr_access_range[i] && 169 addr <= slcr_access_range[i+1]) { 170 static vaddr_t va; 171 172 if (!va) 173 va = (vaddr_t)phys_to_virt(SLCR_BASE, 174 MEM_AREA_IO_SEC, 175 addr + 176 sizeof(uint32_t)); 177 io_write32(va + addr, val); 178 return OPTEE_SMC_RETURN_OK; 179 } 180 } 181 return OPTEE_SMC_RETURN_EBADADDR; 182 } 183 184 static uint32_t read_slcr(uint32_t addr, uint32_t *val) 185 { 186 uint32_t i; 187 188 for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { 189 if (addr >= slcr_access_range[i] && 190 addr <= slcr_access_range[i+1]) { 191 static vaddr_t va; 192 193 if (!va) 194 va = (vaddr_t)phys_to_virt(SLCR_BASE, 195 MEM_AREA_IO_SEC, 196 addr + 197 sizeof(uint32_t)); 198 *val = io_read32(va + addr); 199 return OPTEE_SMC_RETURN_OK; 200 } 201 } 202 return OPTEE_SMC_RETURN_EBADADDR; 203 } 204 205 /* Overriding the default __weak tee_entry_fast() */ 206 void tee_entry_fast(struct thread_smc_args *args) 207 { 208 switch (args->a0) { 209 case ZYNQ7K_SMC_SLCR_WRITE: 210 args->a0 = write_slcr(args->a1, args->a2); 211 break; 212 case ZYNQ7K_SMC_SLCR_READ: 213 args->a0 = read_slcr(args->a1, &args->a2); 214 break; 215 default: 216 __tee_entry_fast(args); 217 break; 218 } 219 } 220