1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * All rights reserved. 4 * Copyright (c) 2016, Wind River Systems. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <arm32.h> 31 #include <console.h> 32 #include <drivers/cdns_uart.h> 33 #include <drivers/gic.h> 34 #include <io.h> 35 #include <kernel/generic_boot.h> 36 #include <kernel/misc.h> 37 #include <kernel/panic.h> 38 #include <kernel/pm_stubs.h> 39 #include <kernel/tz_ssvce_pl310.h> 40 #include <mm/core_mmu.h> 41 #include <mm/core_memprot.h> 42 #include <platform_config.h> 43 #include <platform_smc.h> 44 #include <stdint.h> 45 #include <tee/entry_fast.h> 46 #include <tee/entry_std.h> 47 48 static void main_fiq(void); 49 static void platform_tee_entry_fast(struct thread_smc_args *args); 50 51 static const struct thread_handlers handlers = { 52 .std_smc = tee_entry_std, 53 .fast_smc = platform_tee_entry_fast, 54 .fiq = main_fiq, 55 .cpu_on = pm_panic, 56 .cpu_off = pm_panic, 57 .cpu_suspend = pm_panic, 58 .cpu_resume = pm_panic, 59 .system_off = pm_panic, 60 .system_reset = pm_panic, 61 }; 62 63 static struct gic_data gic_data; 64 65 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CORE_MMU_DEVICE_SIZE); 66 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE); 67 register_phys_mem(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_DEVICE_SIZE); 68 register_phys_mem(MEM_AREA_IO_SEC, SLCR_BASE, CORE_MMU_DEVICE_SIZE); 69 70 const struct thread_handlers *generic_boot_get_handlers(void) 71 { 72 return &handlers; 73 } 74 75 static void main_fiq(void) 76 { 77 panic(); 78 } 79 80 void plat_cpu_reset_late(void) 81 { 82 if (!get_core_pos()) { 83 /* primary core */ 84 #if defined(CFG_BOOT_SECONDARY_REQUEST) 85 /* set secondary entry address and release core */ 86 write32(CFG_TEE_LOAD_ADDR, SECONDARY_ENTRY_DROP); 87 dsb(); 88 sev(); 89 #endif 90 91 /* SCU config */ 92 write32(SCU_INV_CTRL_INIT, SCU_BASE + SCU_INV_SEC); 93 write32(SCU_SAC_CTRL_INIT, SCU_BASE + SCU_SAC); 94 write32(SCU_NSAC_CTRL_INIT, SCU_BASE + SCU_NSAC); 95 96 /* SCU enable */ 97 write32(read32(SCU_BASE + SCU_CTRL) | 0x1, 98 SCU_BASE + SCU_CTRL); 99 100 /* NS Access control */ 101 write32(ACCESS_BITS_ALL, SECURITY2_SDIO0); 102 write32(ACCESS_BITS_ALL, SECURITY3_SDIO1); 103 write32(ACCESS_BITS_ALL, SECURITY4_QSPI); 104 write32(ACCESS_BITS_ALL, SECURITY6_APB_SLAVES); 105 106 write32(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK); 107 108 write32(ACCESS_BITS_ALL, SLCR_TZ_DDR_RAM); 109 write32(ACCESS_BITS_ALL, SLCR_TZ_DMA_NS); 110 write32(ACCESS_BITS_ALL, SLCR_TZ_DMA_IRQ_NS); 111 write32(ACCESS_BITS_ALL, SLCR_TZ_DMA_PERIPH_NS); 112 write32(ACCESS_BITS_ALL, SLCR_TZ_GEM); 113 write32(ACCESS_BITS_ALL, SLCR_TZ_SDIO); 114 write32(ACCESS_BITS_ALL, SLCR_TZ_USB); 115 116 write32(SLCR_LOCK_MAGIC, SLCR_LOCK); 117 } 118 } 119 120 static vaddr_t console_base(void) 121 { 122 static void *va __early_bss; 123 124 if (cpu_mmu_enabled()) { 125 if (!va) 126 va = phys_to_virt(CONSOLE_UART_BASE, 127 MEM_AREA_IO_NSEC); 128 return (vaddr_t)va; 129 } 130 return CONSOLE_UART_BASE; 131 } 132 133 void console_init(void) 134 { 135 } 136 137 void console_putc(int ch) 138 { 139 if (ch == '\n') 140 cdns_uart_putc('\r', console_base()); 141 cdns_uart_putc(ch, console_base()); 142 } 143 144 void console_flush(void) 145 { 146 cdns_uart_flush(console_base()); 147 } 148 149 vaddr_t pl310_base(void) 150 { 151 static void *va __early_bss; 152 153 if (cpu_mmu_enabled()) { 154 if (!va) 155 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 156 return (vaddr_t)va; 157 } 158 return PL310_BASE; 159 } 160 161 void arm_cl2_config(vaddr_t pl310_base) 162 { 163 /* Disable PL310 */ 164 write32(0, pl310_base + PL310_CTRL); 165 166 /* 167 * Xilinx AR#54190 recommends setting L2C RAM in SLCR 168 * to 0x00020202 for proper cache operations. 169 */ 170 write32(SLCR_L2C_RAM_VALUE, SLCR_L2C_RAM); 171 172 write32(PL310_TAG_RAM_CTRL_INIT, pl310_base + PL310_TAG_RAM_CTRL); 173 write32(PL310_DATA_RAM_CTRL_INIT, pl310_base + PL310_DATA_RAM_CTRL); 174 write32(PL310_AUX_CTRL_INIT, pl310_base + PL310_AUX_CTRL); 175 write32(PL310_PREFETCH_CTRL_INIT, pl310_base + PL310_PREFETCH_CTRL); 176 write32(PL310_POWER_CTRL_INIT, pl310_base + PL310_POWER_CTRL); 177 178 /* invalidate all cache ways */ 179 arm_cl2_invbyway(pl310_base); 180 } 181 182 void arm_cl2_enable(vaddr_t pl310_base) 183 { 184 uint32_t val; 185 186 /* Enable PL310 ctrl -> only set lsb bit */ 187 write32(1, pl310_base + PL310_CTRL); 188 189 /* if L2 FLZW enable, enable in L1 */ 190 val = read32(pl310_base + PL310_AUX_CTRL); 191 if (val & 1) 192 write_actlr(read_actlr() | (1 << 3)); 193 } 194 195 void main_init_gic(void) 196 { 197 vaddr_t gicc_base; 198 vaddr_t gicd_base; 199 200 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 201 MEM_AREA_IO_SEC); 202 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 203 MEM_AREA_IO_SEC); 204 205 if (!gicc_base || !gicd_base) 206 panic(); 207 208 /* Initialize GIC */ 209 gic_init(&gic_data, gicc_base, gicd_base); 210 itr_init(&gic_data.chip); 211 } 212 213 void main_secondary_init_gic(void) 214 { 215 gic_cpu_init(&gic_data); 216 } 217 218 static vaddr_t slcr_access_range[] = { 219 0x004, 0x008, /* lock, unlock */ 220 0x100, 0x1FF, /* PLL */ 221 0x200, 0x2FF, /* Reset */ 222 0xA00, 0xAFF /* L2C */ 223 }; 224 225 static uint32_t write_slcr(uint32_t addr, uint32_t val) 226 { 227 uint32_t i; 228 229 for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { 230 if (addr >= slcr_access_range[i] && 231 addr <= slcr_access_range[i+1]) { 232 static vaddr_t va __early_bss; 233 234 if (!va) 235 va = (vaddr_t)phys_to_virt(SLCR_BASE, 236 MEM_AREA_IO_SEC); 237 write32(val, va + addr); 238 return OPTEE_SMC_RETURN_OK; 239 } 240 } 241 return OPTEE_SMC_RETURN_EBADADDR; 242 } 243 244 static uint32_t read_slcr(uint32_t addr, uint32_t *val) 245 { 246 uint32_t i; 247 248 for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { 249 if (addr >= slcr_access_range[i] && 250 addr <= slcr_access_range[i+1]) { 251 static vaddr_t va __early_bss; 252 253 if (!va) 254 va = (vaddr_t)phys_to_virt(SLCR_BASE, 255 MEM_AREA_IO_SEC); 256 *val = read32(va + addr); 257 return OPTEE_SMC_RETURN_OK; 258 } 259 } 260 return OPTEE_SMC_RETURN_EBADADDR; 261 } 262 263 static void platform_tee_entry_fast(struct thread_smc_args *args) 264 { 265 switch (args->a0) { 266 case ZYNQ7K_SMC_SLCR_WRITE: 267 args->a0 = write_slcr(args->a1, args->a2); 268 break; 269 case ZYNQ7K_SMC_SLCR_READ: 270 args->a0 = read_slcr(args->a1, &args->a2); 271 break; 272 default: 273 tee_entry_fast(args); 274 break; 275 } 276 } 277