1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * All rights reserved. 5 * Copyright (c) 2016, Wind River Systems. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arm32.h> 32 #include <console.h> 33 #include <drivers/cdns_uart.h> 34 #include <drivers/gic.h> 35 #include <io.h> 36 #include <kernel/generic_boot.h> 37 #include <kernel/misc.h> 38 #include <kernel/panic.h> 39 #include <kernel/pm_stubs.h> 40 #include <kernel/tz_ssvce_pl310.h> 41 #include <mm/core_mmu.h> 42 #include <mm/core_memprot.h> 43 #include <platform_config.h> 44 #include <platform_smc.h> 45 #include <stdint.h> 46 #include <tee/entry_fast.h> 47 #include <tee/entry_std.h> 48 49 static const struct thread_handlers handlers = { 50 .cpu_on = pm_panic, 51 .cpu_off = pm_panic, 52 .cpu_suspend = pm_panic, 53 .cpu_resume = pm_panic, 54 .system_off = pm_panic, 55 .system_reset = pm_panic, 56 }; 57 58 static struct gic_data gic_data; 59 static struct cdns_uart_data console_data; 60 61 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 62 CORE_MMU_PGDIR_SIZE); 63 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 64 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_PGDIR_SIZE); 65 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SLCR_BASE, CORE_MMU_PGDIR_SIZE); 66 67 const struct thread_handlers *generic_boot_get_handlers(void) 68 { 69 return &handlers; 70 } 71 72 void plat_primary_init_early(void) 73 { 74 /* primary core */ 75 #if defined(CFG_BOOT_SECONDARY_REQUEST) 76 /* set secondary entry address and release core */ 77 io_write32(SECONDARY_ENTRY_DROP, TEE_LOAD_ADDR); 78 dsb(); 79 sev(); 80 #endif 81 82 /* SCU config */ 83 io_write32(SCU_BASE + SCU_INV_SEC, SCU_INV_CTRL_INIT); 84 io_write32(SCU_BASE + SCU_SAC, SCU_SAC_CTRL_INIT); 85 io_write32(SCU_BASE + SCU_NSAC, SCU_NSAC_CTRL_INIT); 86 87 /* SCU enable */ 88 io_setbits32(SCU_BASE + SCU_CTRL, 0x1); 89 90 /* NS Access control */ 91 io_write32(SECURITY2_SDIO0, ACCESS_BITS_ALL); 92 io_write32(SECURITY3_SDIO1, ACCESS_BITS_ALL); 93 io_write32(SECURITY4_QSPI, ACCESS_BITS_ALL); 94 io_write32(SECURITY6_APB_SLAVES, ACCESS_BITS_ALL); 95 96 io_write32(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK); 97 98 io_write32(SLCR_TZ_DDR_RAM, ACCESS_BITS_ALL); 99 io_write32(SLCR_TZ_DMA_NS, ACCESS_BITS_ALL); 100 io_write32(SLCR_TZ_DMA_IRQ_NS, ACCESS_BITS_ALL); 101 io_write32(SLCR_TZ_DMA_PERIPH_NS, ACCESS_BITS_ALL); 102 io_write32(SLCR_TZ_GEM, ACCESS_BITS_ALL); 103 io_write32(SLCR_TZ_SDIO, ACCESS_BITS_ALL); 104 io_write32(SLCR_TZ_USB, ACCESS_BITS_ALL); 105 106 io_write32(SLCR_LOCK, SLCR_LOCK_MAGIC); 107 } 108 109 void console_init(void) 110 { 111 cdns_uart_init(&console_data, CONSOLE_UART_BASE, 0, 0); 112 register_serial_console(&console_data.chip); 113 } 114 115 vaddr_t pl310_base(void) 116 { 117 static void *va; 118 119 if (cpu_mmu_enabled()) { 120 if (!va) 121 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 122 return (vaddr_t)va; 123 } 124 return PL310_BASE; 125 } 126 127 void arm_cl2_config(vaddr_t pl310_base) 128 { 129 /* Disable PL310 */ 130 io_write32(pl310_base + PL310_CTRL, 0); 131 132 /* 133 * Xilinx AR#54190 recommends setting L2C RAM in SLCR 134 * to 0x00020202 for proper cache operations. 135 */ 136 io_write32(SLCR_L2C_RAM, SLCR_L2C_RAM_VALUE); 137 138 io_write32(pl310_base + PL310_TAG_RAM_CTRL, PL310_TAG_RAM_CTRL_INIT); 139 io_write32(pl310_base + PL310_DATA_RAM_CTRL, PL310_DATA_RAM_CTRL_INIT); 140 io_write32(pl310_base + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); 141 io_write32(pl310_base + PL310_PREFETCH_CTRL, PL310_PREFETCH_CTRL_INIT); 142 io_write32(pl310_base + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); 143 144 /* invalidate all cache ways */ 145 arm_cl2_invbyway(pl310_base); 146 } 147 148 void arm_cl2_enable(vaddr_t pl310_base) 149 { 150 uint32_t val; 151 152 /* Enable PL310 ctrl -> only set lsb bit */ 153 io_write32(pl310_base + PL310_CTRL, 1); 154 155 /* if L2 FLZW enable, enable in L1 */ 156 val = io_read32(pl310_base + PL310_AUX_CTRL); 157 if (val & 1) 158 write_actlr(read_actlr() | (1 << 3)); 159 } 160 161 void main_init_gic(void) 162 { 163 vaddr_t gicc_base; 164 vaddr_t gicd_base; 165 166 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 167 MEM_AREA_IO_SEC); 168 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 169 MEM_AREA_IO_SEC); 170 171 if (!gicc_base || !gicd_base) 172 panic(); 173 174 /* Initialize GIC */ 175 gic_init(&gic_data, gicc_base, gicd_base); 176 itr_init(&gic_data.chip); 177 } 178 179 void main_secondary_init_gic(void) 180 { 181 gic_cpu_init(&gic_data); 182 } 183 184 static vaddr_t slcr_access_range[] = { 185 0x004, 0x008, /* lock, unlock */ 186 0x100, 0x1FF, /* PLL */ 187 0x200, 0x2FF, /* Reset */ 188 0xA00, 0xAFF /* L2C */ 189 }; 190 191 static uint32_t write_slcr(uint32_t addr, uint32_t val) 192 { 193 uint32_t i; 194 195 for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { 196 if (addr >= slcr_access_range[i] && 197 addr <= slcr_access_range[i+1]) { 198 static vaddr_t va; 199 200 if (!va) 201 va = (vaddr_t)phys_to_virt(SLCR_BASE, 202 MEM_AREA_IO_SEC); 203 io_write32(va + addr, val); 204 return OPTEE_SMC_RETURN_OK; 205 } 206 } 207 return OPTEE_SMC_RETURN_EBADADDR; 208 } 209 210 static uint32_t read_slcr(uint32_t addr, uint32_t *val) 211 { 212 uint32_t i; 213 214 for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { 215 if (addr >= slcr_access_range[i] && 216 addr <= slcr_access_range[i+1]) { 217 static vaddr_t va; 218 219 if (!va) 220 va = (vaddr_t)phys_to_virt(SLCR_BASE, 221 MEM_AREA_IO_SEC); 222 *val = io_read32(va + addr); 223 return OPTEE_SMC_RETURN_OK; 224 } 225 } 226 return OPTEE_SMC_RETURN_EBADADDR; 227 } 228 229 /* Overriding the default __weak tee_entry_fast() */ 230 void tee_entry_fast(struct thread_smc_args *args) 231 { 232 switch (args->a0) { 233 case ZYNQ7K_SMC_SLCR_WRITE: 234 args->a0 = write_slcr(args->a1, args->a2); 235 break; 236 case ZYNQ7K_SMC_SLCR_READ: 237 args->a0 = read_slcr(args->a1, &args->a2); 238 break; 239 default: 240 __tee_entry_fast(args); 241 break; 242 } 243 } 244