1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * All rights reserved. 5 * Copyright (c) 2016, Wind River Systems. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arm32.h> 32 #include <console.h> 33 #include <drivers/cdns_uart.h> 34 #include <drivers/gic.h> 35 #include <io.h> 36 #include <kernel/generic_boot.h> 37 #include <kernel/misc.h> 38 #include <kernel/panic.h> 39 #include <kernel/pm_stubs.h> 40 #include <kernel/tz_ssvce_pl310.h> 41 #include <mm/core_mmu.h> 42 #include <mm/core_memprot.h> 43 #include <platform_config.h> 44 #include <platform_smc.h> 45 #include <stdint.h> 46 #include <tee/entry_fast.h> 47 #include <tee/entry_std.h> 48 49 static void main_fiq(void); 50 static void platform_tee_entry_fast(struct thread_smc_args *args); 51 52 static const struct thread_handlers handlers = { 53 .std_smc = tee_entry_std, 54 .fast_smc = platform_tee_entry_fast, 55 .nintr = main_fiq, 56 .cpu_on = pm_panic, 57 .cpu_off = pm_panic, 58 .cpu_suspend = pm_panic, 59 .cpu_resume = pm_panic, 60 .system_off = pm_panic, 61 .system_reset = pm_panic, 62 }; 63 64 static struct gic_data gic_data; 65 static struct cdns_uart_data console_data; 66 67 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 68 CORE_MMU_PGDIR_SIZE); 69 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 70 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_PGDIR_SIZE); 71 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SLCR_BASE, CORE_MMU_PGDIR_SIZE); 72 73 const struct thread_handlers *generic_boot_get_handlers(void) 74 { 75 return &handlers; 76 } 77 78 static void main_fiq(void) 79 { 80 panic(); 81 } 82 83 void plat_cpu_reset_late(void) 84 { 85 if (!get_core_pos()) { 86 /* primary core */ 87 #if defined(CFG_BOOT_SECONDARY_REQUEST) 88 /* set secondary entry address and release core */ 89 write32(TEE_LOAD_ADDR, SECONDARY_ENTRY_DROP); 90 dsb(); 91 sev(); 92 #endif 93 94 /* SCU config */ 95 write32(SCU_INV_CTRL_INIT, SCU_BASE + SCU_INV_SEC); 96 write32(SCU_SAC_CTRL_INIT, SCU_BASE + SCU_SAC); 97 write32(SCU_NSAC_CTRL_INIT, SCU_BASE + SCU_NSAC); 98 99 /* SCU enable */ 100 write32(read32(SCU_BASE + SCU_CTRL) | 0x1, 101 SCU_BASE + SCU_CTRL); 102 103 /* NS Access control */ 104 write32(ACCESS_BITS_ALL, SECURITY2_SDIO0); 105 write32(ACCESS_BITS_ALL, SECURITY3_SDIO1); 106 write32(ACCESS_BITS_ALL, SECURITY4_QSPI); 107 write32(ACCESS_BITS_ALL, SECURITY6_APB_SLAVES); 108 109 write32(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK); 110 111 write32(ACCESS_BITS_ALL, SLCR_TZ_DDR_RAM); 112 write32(ACCESS_BITS_ALL, SLCR_TZ_DMA_NS); 113 write32(ACCESS_BITS_ALL, SLCR_TZ_DMA_IRQ_NS); 114 write32(ACCESS_BITS_ALL, SLCR_TZ_DMA_PERIPH_NS); 115 write32(ACCESS_BITS_ALL, SLCR_TZ_GEM); 116 write32(ACCESS_BITS_ALL, SLCR_TZ_SDIO); 117 write32(ACCESS_BITS_ALL, SLCR_TZ_USB); 118 119 write32(SLCR_LOCK_MAGIC, SLCR_LOCK); 120 } 121 } 122 123 void console_init(void) 124 { 125 cdns_uart_init(&console_data, CONSOLE_UART_BASE, 0, 0); 126 register_serial_console(&console_data.chip); 127 } 128 129 vaddr_t pl310_base(void) 130 { 131 static void *va; 132 133 if (cpu_mmu_enabled()) { 134 if (!va) 135 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 136 return (vaddr_t)va; 137 } 138 return PL310_BASE; 139 } 140 141 void arm_cl2_config(vaddr_t pl310_base) 142 { 143 /* Disable PL310 */ 144 write32(0, pl310_base + PL310_CTRL); 145 146 /* 147 * Xilinx AR#54190 recommends setting L2C RAM in SLCR 148 * to 0x00020202 for proper cache operations. 149 */ 150 write32(SLCR_L2C_RAM_VALUE, SLCR_L2C_RAM); 151 152 write32(PL310_TAG_RAM_CTRL_INIT, pl310_base + PL310_TAG_RAM_CTRL); 153 write32(PL310_DATA_RAM_CTRL_INIT, pl310_base + PL310_DATA_RAM_CTRL); 154 write32(PL310_AUX_CTRL_INIT, pl310_base + PL310_AUX_CTRL); 155 write32(PL310_PREFETCH_CTRL_INIT, pl310_base + PL310_PREFETCH_CTRL); 156 write32(PL310_POWER_CTRL_INIT, pl310_base + PL310_POWER_CTRL); 157 158 /* invalidate all cache ways */ 159 arm_cl2_invbyway(pl310_base); 160 } 161 162 void arm_cl2_enable(vaddr_t pl310_base) 163 { 164 uint32_t val; 165 166 /* Enable PL310 ctrl -> only set lsb bit */ 167 write32(1, pl310_base + PL310_CTRL); 168 169 /* if L2 FLZW enable, enable in L1 */ 170 val = read32(pl310_base + PL310_AUX_CTRL); 171 if (val & 1) 172 write_actlr(read_actlr() | (1 << 3)); 173 } 174 175 void main_init_gic(void) 176 { 177 vaddr_t gicc_base; 178 vaddr_t gicd_base; 179 180 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 181 MEM_AREA_IO_SEC); 182 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 183 MEM_AREA_IO_SEC); 184 185 if (!gicc_base || !gicd_base) 186 panic(); 187 188 /* Initialize GIC */ 189 gic_init(&gic_data, gicc_base, gicd_base); 190 itr_init(&gic_data.chip); 191 } 192 193 void main_secondary_init_gic(void) 194 { 195 gic_cpu_init(&gic_data); 196 } 197 198 static vaddr_t slcr_access_range[] = { 199 0x004, 0x008, /* lock, unlock */ 200 0x100, 0x1FF, /* PLL */ 201 0x200, 0x2FF, /* Reset */ 202 0xA00, 0xAFF /* L2C */ 203 }; 204 205 static uint32_t write_slcr(uint32_t addr, uint32_t val) 206 { 207 uint32_t i; 208 209 for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { 210 if (addr >= slcr_access_range[i] && 211 addr <= slcr_access_range[i+1]) { 212 static vaddr_t va; 213 214 if (!va) 215 va = (vaddr_t)phys_to_virt(SLCR_BASE, 216 MEM_AREA_IO_SEC); 217 write32(val, va + addr); 218 return OPTEE_SMC_RETURN_OK; 219 } 220 } 221 return OPTEE_SMC_RETURN_EBADADDR; 222 } 223 224 static uint32_t read_slcr(uint32_t addr, uint32_t *val) 225 { 226 uint32_t i; 227 228 for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { 229 if (addr >= slcr_access_range[i] && 230 addr <= slcr_access_range[i+1]) { 231 static vaddr_t va; 232 233 if (!va) 234 va = (vaddr_t)phys_to_virt(SLCR_BASE, 235 MEM_AREA_IO_SEC); 236 *val = read32(va + addr); 237 return OPTEE_SMC_RETURN_OK; 238 } 239 } 240 return OPTEE_SMC_RETURN_EBADADDR; 241 } 242 243 static void platform_tee_entry_fast(struct thread_smc_args *args) 244 { 245 switch (args->a0) { 246 case ZYNQ7K_SMC_SLCR_WRITE: 247 args->a0 = write_slcr(args->a1, args->a2); 248 break; 249 case ZYNQ7K_SMC_SLCR_READ: 250 args->a0 = read_slcr(args->a1, &args->a2); 251 break; 252 default: 253 tee_entry_fast(args); 254 break; 255 } 256 } 257