1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016-2023, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #include <arm.h> 8 #include <config.h> 9 #include <console.h> 10 #include <drivers/gic.h> 11 #include <drivers/hfic.h> 12 #include <drivers/pl011.h> 13 #include <drivers/tzc400.h> 14 #include <initcall.h> 15 #include <keep.h> 16 #include <kernel/boot.h> 17 #include <kernel/interrupt.h> 18 #include <kernel/misc.h> 19 #include <kernel/notif.h> 20 #include <kernel/panic.h> 21 #include <kernel/thread_spmc.h> 22 #include <mm/core_memprot.h> 23 #include <mm/core_mmu.h> 24 #include <platform_config.h> 25 #include <sm/psci.h> 26 #include <stdint.h> 27 #include <trace.h> 28 29 static struct pl011_data console_data __nex_bss; 30 31 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 32 #if defined(PLATFORM_FLAVOR_fvp) 33 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE); 34 #endif 35 #if defined(PLATFORM_FLAVOR_qemu_virt) 36 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE); 37 #endif 38 #ifdef DRAM0_BASE 39 register_ddr(DRAM0_BASE, DRAM0_SIZE); 40 #endif 41 #ifdef DRAM1_BASE 42 register_ddr(DRAM1_BASE, DRAM1_SIZE); 43 #endif 44 45 #ifdef CFG_GIC 46 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE); 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 48 #ifdef GIC_REDIST_BASE 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_REDIST_BASE, GIC_REDIST_SIZE); 50 #endif 51 52 void boot_primary_init_intc(void) 53 { 54 #ifdef GIC_REDIST_BASE 55 gic_init_v3(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET, 56 GIC_REDIST_BASE); 57 #else 58 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 59 #endif 60 if (IS_ENABLED(CFG_CORE_SEL1_SPMC) && 61 IS_ENABLED(CFG_CORE_ASYNC_NOTIF)) { 62 size_t it = CFG_CORE_ASYNC_NOTIF_GIC_INTID; 63 64 if (it >= GIC_SGI_SEC_BASE && it <= GIC_SGI_SEC_MAX) 65 gic_init_donate_sgi_to_ns(it); 66 thread_spmc_set_async_notif_intid(it); 67 } 68 } 69 70 void boot_secondary_init_intc(void) 71 { 72 gic_init_per_cpu(); 73 } 74 #endif /*CFG_GIC*/ 75 76 #ifdef CFG_CORE_HAFNIUM_INTC 77 void boot_primary_init_intc(void) 78 { 79 hfic_init(); 80 } 81 #endif 82 83 void plat_console_init(void) 84 { 85 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 86 CONSOLE_BAUDRATE); 87 register_serial_console(&console_data.chip); 88 } 89 90 #if (defined(CFG_GIC) || defined(CFG_CORE_HAFNIUM_INTC)) && \ 91 defined(IT_CONSOLE_UART) && \ 92 !defined(CFG_NS_VIRTUALIZATION) && \ 93 !(defined(CFG_WITH_ARM_TRUSTED_FW) && defined(CFG_ARM_GICV2)) && \ 94 !defined(CFG_SEMIHOSTING_CONSOLE) 95 /* 96 * This cannot be enabled with TF-A and GICv3 because TF-A then need to 97 * assign the interrupt number of the UART to OP-TEE (S-EL1). Currently 98 * there's no way of TF-A to know which interrupts that OP-TEE will serve. 99 * If TF-A doesn't assign the interrupt we're enabling below to OP-TEE it 100 * will hang in EL3 since the interrupt will just be delivered again and 101 * again. 102 */ 103 104 static void read_console(void) 105 { 106 struct serial_chip *cons = &console_data.chip; 107 108 if (!cons->ops->getchar || !cons->ops->have_rx_data) 109 return; 110 111 while (cons->ops->have_rx_data(cons)) { 112 int ch __maybe_unused = cons->ops->getchar(cons); 113 114 DMSG("got 0x%x", ch); 115 } 116 } 117 118 static enum itr_return console_itr_cb(struct itr_handler *hdl __unused) 119 { 120 if (notif_async_is_started()) { 121 /* 122 * Asynchronous notifications are enabled, lets read from 123 * uart in the bottom half instead. 124 */ 125 console_data.chip.ops->rx_intr_disable(&console_data.chip); 126 notif_send_async(NOTIF_VALUE_DO_BOTTOM_HALF); 127 } else { 128 read_console(); 129 } 130 return ITRR_HANDLED; 131 } 132 133 static struct itr_handler console_itr = { 134 .it = IT_CONSOLE_UART, 135 .flags = ITRF_TRIGGER_LEVEL, 136 .handler = console_itr_cb, 137 }; 138 DECLARE_KEEP_PAGER(console_itr); 139 140 static void atomic_console_notif(struct notif_driver *ndrv __unused, 141 enum notif_event ev __maybe_unused) 142 { 143 DMSG("Asynchronous notifications started, event %d", (int)ev); 144 } 145 DECLARE_KEEP_PAGER(atomic_console_notif); 146 147 static void yielding_console_notif(struct notif_driver *ndrv __unused, 148 enum notif_event ev) 149 { 150 switch (ev) { 151 case NOTIF_EVENT_DO_BOTTOM_HALF: 152 read_console(); 153 console_data.chip.ops->rx_intr_enable(&console_data.chip); 154 break; 155 case NOTIF_EVENT_STOPPED: 156 DMSG("Asynchronous notifications stopped"); 157 console_data.chip.ops->rx_intr_enable(&console_data.chip); 158 break; 159 default: 160 EMSG("Unknown event %d", (int)ev); 161 } 162 } 163 164 struct notif_driver console_notif = { 165 .atomic_cb = atomic_console_notif, 166 .yielding_cb = yielding_console_notif, 167 }; 168 169 static TEE_Result init_console_itr(void) 170 { 171 TEE_Result res = TEE_ERROR_GENERIC; 172 bool have_itr_ctrl = console_data.chip.ops->rx_intr_enable && 173 console_data.chip.ops->rx_intr_disable; 174 175 res = interrupt_add_handler_with_chip(interrupt_get_main_chip(), 176 &console_itr); 177 if (res) 178 return res; 179 180 interrupt_enable(console_itr.chip, console_itr.it); 181 182 if (IS_ENABLED(CFG_CORE_ASYNC_NOTIF) && have_itr_ctrl) 183 notif_register_driver(&console_notif); 184 return TEE_SUCCESS; 185 } 186 driver_init(init_console_itr); 187 #endif 188 189 #ifdef CFG_TZC400 190 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 191 192 static TEE_Result init_tzc400(void) 193 { 194 void *va; 195 196 DMSG("Initializing TZC400"); 197 198 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC, TZC400_REG_SIZE); 199 if (!va) { 200 EMSG("TZC400 not mapped"); 201 panic(); 202 } 203 204 tzc_init((vaddr_t)va); 205 tzc_dump_state(); 206 207 return TEE_SUCCESS; 208 } 209 210 service_init(init_tzc400); 211 #endif /*CFG_TZC400*/ 212 213 #if defined(PLATFORM_FLAVOR_qemu_virt) 214 static void release_secondary_early_hpen(size_t pos) 215 { 216 struct mailbox { 217 uint64_t ep; 218 uint64_t hpen[]; 219 } *mailbox; 220 221 if (cpu_mmu_enabled()) 222 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC, 223 SECRAM_COHERENT_SIZE); 224 else 225 mailbox = (void *)SECRAM_BASE; 226 227 if (!mailbox) 228 panic(); 229 230 mailbox->ep = TEE_LOAD_ADDR; 231 dsb_ishst(); 232 mailbox->hpen[pos] = 1; 233 dsb_ishst(); 234 sev(); 235 } 236 237 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 238 { 239 size_t pos = get_core_pos_mpidr(core_id); 240 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 241 242 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 243 return PSCI_RET_INVALID_PARAMETERS; 244 245 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 246 247 if (core_is_released[pos]) { 248 EMSG("core %zu already released", pos); 249 return PSCI_RET_DENIED; 250 } 251 core_is_released[pos] = true; 252 253 boot_set_core_ns_entry(pos, entry, context_id); 254 release_secondary_early_hpen(pos); 255 256 return PSCI_RET_SUCCESS; 257 } 258 #endif /*PLATFORM_FLAVOR_qemu_virt*/ 259