1 /* 2 * Copyright (c) 2016, Linaro Limited 3 * Copyright (c) 2014, STMicroelectronics International N.V. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <platform_config.h> 30 31 #include <stdint.h> 32 #include <string.h> 33 34 #include <drivers/gic.h> 35 #include <drivers/pl011.h> 36 #include <drivers/tzc400.h> 37 38 #include <arm.h> 39 #include <kernel/generic_boot.h> 40 #include <kernel/pm_stubs.h> 41 #include <trace.h> 42 #include <kernel/misc.h> 43 #include <kernel/panic.h> 44 #include <kernel/tee_time.h> 45 #include <tee/entry_fast.h> 46 #include <tee/entry_std.h> 47 #include <mm/core_memprot.h> 48 #include <mm/core_mmu.h> 49 #include <console.h> 50 #include <keep.h> 51 #include <initcall.h> 52 53 static void main_fiq(void); 54 55 static const struct thread_handlers handlers = { 56 .std_smc = tee_entry_std, 57 .fast_smc = tee_entry_fast, 58 .nintr = main_fiq, 59 #if defined(CFG_WITH_ARM_TRUSTED_FW) 60 .cpu_on = cpu_on_handler, 61 .cpu_off = pm_do_nothing, 62 .cpu_suspend = pm_do_nothing, 63 .cpu_resume = pm_do_nothing, 64 .system_off = pm_do_nothing, 65 .system_reset = pm_do_nothing, 66 #else 67 .cpu_on = pm_panic, 68 .cpu_off = pm_panic, 69 .cpu_suspend = pm_panic, 70 .cpu_resume = pm_panic, 71 .system_off = pm_panic, 72 .system_reset = pm_panic, 73 #endif 74 }; 75 76 static struct gic_data gic_data; 77 static struct pl011_data console_data; 78 79 register_phys_mem(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 80 register_nsec_ddr(DRAM0_BASE, DRAM0_SIZE); 81 82 const struct thread_handlers *generic_boot_get_handlers(void) 83 { 84 return &handlers; 85 } 86 87 #ifdef GIC_BASE 88 89 register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 90 register_phys_mem(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); 91 92 void main_init_gic(void) 93 { 94 vaddr_t gicc_base; 95 vaddr_t gicd_base; 96 97 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 98 MEM_AREA_IO_SEC); 99 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 100 MEM_AREA_IO_SEC); 101 if (!gicc_base || !gicd_base) 102 panic(); 103 104 #if defined(PLATFORM_FLAVOR_fvp) || defined(PLATFORM_FLAVOR_juno) || \ 105 defined(PLATFORM_FLAVOR_qemu_armv8a) 106 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 107 gic_init_base_addr(&gic_data, gicc_base, gicd_base); 108 #else 109 /* Initialize GIC */ 110 gic_init(&gic_data, gicc_base, gicd_base); 111 #endif 112 itr_init(&gic_data.chip); 113 } 114 #endif 115 116 static void main_fiq(void) 117 { 118 gic_it_handle(&gic_data); 119 } 120 121 void console_init(void) 122 { 123 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 124 CONSOLE_BAUDRATE); 125 register_serial_console(&console_data.chip); 126 } 127 128 #ifdef IT_CONSOLE_UART 129 static enum itr_return console_itr_cb(struct itr_handler *h __unused) 130 { 131 struct serial_chip *cons = &console_data.chip; 132 133 while (cons->ops->have_rx_data(cons)) { 134 int ch __maybe_unused = cons->ops->getchar(cons); 135 136 DMSG("cpu %zu: got 0x%x", get_core_pos(), ch); 137 } 138 return ITRR_HANDLED; 139 } 140 141 static struct itr_handler console_itr = { 142 .it = IT_CONSOLE_UART, 143 .flags = ITRF_TRIGGER_LEVEL, 144 .handler = console_itr_cb, 145 }; 146 KEEP_PAGER(console_itr); 147 148 static TEE_Result init_console_itr(void) 149 { 150 itr_add(&console_itr); 151 itr_enable(IT_CONSOLE_UART); 152 return TEE_SUCCESS; 153 } 154 driver_init(init_console_itr); 155 #endif 156 157 #ifdef CFG_TZC400 158 register_phys_mem(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 159 160 static TEE_Result init_tzc400(void) 161 { 162 void *va; 163 164 DMSG("Initializing TZC400"); 165 166 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC); 167 if (!va) { 168 EMSG("TZC400 not mapped"); 169 panic(); 170 } 171 172 tzc_init((vaddr_t)va); 173 tzc_dump_state(); 174 175 return TEE_SUCCESS; 176 } 177 178 service_init(init_tzc400); 179 #endif /*CFG_TZC400*/ 180