1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016-2020, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #include <arm.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/pl011.h> 11 #include <drivers/tzc400.h> 12 #include <initcall.h> 13 #include <keep.h> 14 #include <kernel/boot.h> 15 #include <kernel/interrupt.h> 16 #include <kernel/misc.h> 17 #include <kernel/notif.h> 18 #include <kernel/panic.h> 19 #include <kernel/spinlock.h> 20 #include <kernel/tee_time.h> 21 #include <mm/core_memprot.h> 22 #include <mm/core_mmu.h> 23 #include <platform_config.h> 24 #include <sm/psci.h> 25 #include <stdint.h> 26 #include <string.h> 27 #include <trace.h> 28 29 static struct gic_data gic_data __nex_bss; 30 static struct pl011_data console_data __nex_bss; 31 32 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 33 #if defined(PLATFORM_FLAVOR_fvp) 34 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE); 35 #endif 36 #if defined(PLATFORM_FLAVOR_qemu_virt) 37 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE); 38 #endif 39 #ifdef DRAM0_BASE 40 register_ddr(DRAM0_BASE, DRAM0_SIZE); 41 #endif 42 #ifdef DRAM1_BASE 43 register_ddr(DRAM1_BASE, DRAM1_SIZE); 44 #endif 45 46 #ifdef GIC_BASE 47 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); 50 51 void main_init_gic(void) 52 { 53 #if defined(CFG_WITH_ARM_TRUSTED_FW) 54 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 55 gic_init_base_addr(&gic_data, GIC_BASE + GICC_OFFSET, 56 GIC_BASE + GICD_OFFSET); 57 #else 58 gic_init(&gic_data, GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 59 #endif 60 itr_init(&gic_data.chip); 61 } 62 63 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 64 void main_secondary_init_gic(void) 65 { 66 gic_cpu_init(&gic_data); 67 } 68 #endif 69 70 #endif 71 72 void itr_core_handler(void) 73 { 74 gic_it_handle(&gic_data); 75 } 76 77 void console_init(void) 78 { 79 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 80 CONSOLE_BAUDRATE); 81 register_serial_console(&console_data.chip); 82 } 83 84 #if defined(IT_CONSOLE_UART) && !defined(CFG_VIRTUALIZATION) && \ 85 !(defined(CFG_WITH_ARM_TRUSTED_FW) && defined(CFG_ARM_GICV2)) 86 /* 87 * This cannot be enabled with TF-A and GICv3 because TF-A then need to 88 * assign the interrupt number of the UART to OP-TEE (S-EL1). Currently 89 * there's no way of TF-A to know which interrupts that OP-TEE will serve. 90 * If TF-A doesn't assign the interrupt we're enabling below to OP-TEE it 91 * will hang in EL3 since the interrupt will just be delivered again and 92 * again. 93 */ 94 95 static void read_console(void) 96 { 97 struct serial_chip *cons = &console_data.chip; 98 99 while (cons->ops->have_rx_data(cons)) { 100 int ch __maybe_unused = cons->ops->getchar(cons); 101 102 DMSG("got 0x%x", ch); 103 } 104 } 105 106 static enum itr_return console_itr_cb(struct itr_handler *h __maybe_unused) 107 { 108 if (notif_async_is_started()) { 109 /* 110 * Asynchronous notifications are enabled, lets read from 111 * uart in the bottom half instead. 112 */ 113 itr_disable(IT_CONSOLE_UART); 114 notif_send_async(NOTIF_VALUE_DO_BOTTOM_HALF); 115 } else { 116 read_console(); 117 } 118 return ITRR_HANDLED; 119 } 120 121 static struct itr_handler console_itr = { 122 .it = IT_CONSOLE_UART, 123 .flags = ITRF_TRIGGER_LEVEL, 124 .handler = console_itr_cb, 125 }; 126 DECLARE_KEEP_PAGER(console_itr); 127 128 static void atomic_console_notif(struct notif_driver *ndrv __unused, 129 enum notif_event ev __maybe_unused) 130 { 131 DMSG("Asynchronous notifications started, event %d", (int)ev); 132 } 133 DECLARE_KEEP_PAGER(atomic_console_notif); 134 135 static void yielding_console_notif(struct notif_driver *ndrv __unused, 136 enum notif_event ev) 137 { 138 switch (ev) { 139 case NOTIF_EVENT_DO_BOTTOM_HALF: 140 read_console(); 141 itr_enable(IT_CONSOLE_UART); 142 break; 143 case NOTIF_EVENT_STOPPED: 144 DMSG("Asynchronous notifications stopped"); 145 itr_enable(IT_CONSOLE_UART); 146 break; 147 default: 148 EMSG("Unknown event %d", (int)ev); 149 } 150 } 151 152 struct notif_driver console_notif = { 153 .atomic_cb = atomic_console_notif, 154 .yielding_cb = yielding_console_notif, 155 }; 156 157 static TEE_Result init_console_itr(void) 158 { 159 itr_add(&console_itr); 160 itr_enable(IT_CONSOLE_UART); 161 if (IS_ENABLED(CFG_CORE_ASYNC_NOTIF)) 162 notif_register_driver(&console_notif); 163 return TEE_SUCCESS; 164 } 165 driver_init(init_console_itr); 166 #endif 167 168 #ifdef CFG_TZC400 169 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 170 171 static TEE_Result init_tzc400(void) 172 { 173 void *va; 174 175 DMSG("Initializing TZC400"); 176 177 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC, TZC400_REG_SIZE); 178 if (!va) { 179 EMSG("TZC400 not mapped"); 180 panic(); 181 } 182 183 tzc_init((vaddr_t)va); 184 tzc_dump_state(); 185 186 return TEE_SUCCESS; 187 } 188 189 service_init(init_tzc400); 190 #endif /*CFG_TZC400*/ 191 192 #if defined(PLATFORM_FLAVOR_qemu_virt) 193 static void release_secondary_early_hpen(size_t pos) 194 { 195 struct mailbox { 196 uint64_t ep; 197 uint64_t hpen[]; 198 } *mailbox; 199 200 if (cpu_mmu_enabled()) 201 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC, 202 SECRAM_COHERENT_SIZE); 203 else 204 mailbox = (void *)SECRAM_BASE; 205 206 if (!mailbox) 207 panic(); 208 209 mailbox->ep = TEE_LOAD_ADDR; 210 dsb_ishst(); 211 mailbox->hpen[pos] = 1; 212 dsb_ishst(); 213 sev(); 214 } 215 216 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 217 { 218 size_t pos = get_core_pos_mpidr(core_id); 219 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 220 221 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 222 return PSCI_RET_INVALID_PARAMETERS; 223 224 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 225 226 if (core_is_released[pos]) { 227 EMSG("core %zu already released", pos); 228 return PSCI_RET_DENIED; 229 } 230 core_is_released[pos] = true; 231 232 boot_set_core_ns_entry(pos, entry, context_id); 233 release_secondary_early_hpen(pos); 234 235 return PSCI_RET_SUCCESS; 236 } 237 #endif /*PLATFORM_FLAVOR_qemu_virt*/ 238