1 /* 2 * Copyright (c) 2016, Linaro Limited 3 * Copyright (c) 2014, STMicroelectronics International N.V. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <platform_config.h> 30 31 #include <stdint.h> 32 #include <string.h> 33 34 #include <drivers/gic.h> 35 #include <drivers/pl011.h> 36 37 #include <arm.h> 38 #include <kernel/generic_boot.h> 39 #include <kernel/pm_stubs.h> 40 #include <trace.h> 41 #include <kernel/misc.h> 42 #include <kernel/tee_time.h> 43 #include <tee/entry_fast.h> 44 #include <tee/entry_std.h> 45 #include <mm/core_memprot.h> 46 #include <mm/core_mmu.h> 47 #include <console.h> 48 #include <keep.h> 49 #include <initcall.h> 50 51 static void main_fiq(void); 52 53 static const struct thread_handlers handlers = { 54 .std_smc = tee_entry_std, 55 .fast_smc = tee_entry_fast, 56 .fiq = main_fiq, 57 #if defined(CFG_WITH_ARM_TRUSTED_FW) 58 .cpu_on = cpu_on_handler, 59 .cpu_off = pm_do_nothing, 60 .cpu_suspend = pm_do_nothing, 61 .cpu_resume = pm_do_nothing, 62 .system_off = pm_do_nothing, 63 .system_reset = pm_do_nothing, 64 #else 65 .cpu_on = pm_panic, 66 .cpu_off = pm_panic, 67 .cpu_suspend = pm_panic, 68 .cpu_resume = pm_panic, 69 .system_off = pm_panic, 70 .system_reset = pm_panic, 71 #endif 72 }; 73 74 static struct gic_data gic_data; 75 76 register_phys_mem(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 77 78 const struct thread_handlers *generic_boot_get_handlers(void) 79 { 80 return &handlers; 81 } 82 83 #ifdef GIC_BASE 84 85 register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 86 register_phys_mem(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); 87 88 void main_init_gic(void) 89 { 90 vaddr_t gicc_base; 91 vaddr_t gicd_base; 92 93 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 94 MEM_AREA_IO_SEC); 95 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 96 MEM_AREA_IO_SEC); 97 TEE_ASSERT(gicc_base && gicd_base); 98 99 #if PLATFORM_FLAVOR_IS(fvp) || PLATFORM_FLAVOR_IS(juno) || \ 100 PLATFORM_FLAVOR_IS(qemu_armv8a) 101 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 102 gic_init_base_addr(&gic_data, gicc_base, gicd_base); 103 #else 104 /* Initialize GIC */ 105 gic_init(&gic_data, gicc_base, gicd_base); 106 #endif 107 itr_init(&gic_data.chip); 108 } 109 #endif 110 111 static void main_fiq(void) 112 { 113 gic_it_handle(&gic_data); 114 } 115 116 static vaddr_t console_base(void) 117 { 118 static void *va; 119 120 if (cpu_mmu_enabled()) { 121 if (!va) 122 va = phys_to_virt(CONSOLE_UART_BASE, MEM_AREA_IO_SEC); 123 return (vaddr_t)va; 124 } 125 return CONSOLE_UART_BASE; 126 } 127 128 void console_init(void) 129 { 130 pl011_init(console_base(), CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE); 131 } 132 133 void console_putc(int ch) 134 { 135 vaddr_t base = console_base(); 136 137 pl011_putc(ch, base); 138 if (ch == '\n') 139 pl011_putc('\r', base); 140 } 141 142 void console_flush(void) 143 { 144 pl011_flush(console_base()); 145 } 146 147 #ifdef IT_CONSOLE_UART 148 static enum itr_return console_itr_cb(struct itr_handler *h __unused) 149 { 150 paddr_t uart_base = console_base(); 151 152 while (pl011_have_rx_data(uart_base)) { 153 int ch __maybe_unused = pl011_getchar(uart_base); 154 155 DMSG("cpu %zu: got 0x%x", get_core_pos(), ch); 156 } 157 return ITRR_HANDLED; 158 } 159 160 static struct itr_handler console_itr = { 161 .it = IT_CONSOLE_UART, 162 .flags = ITRF_TRIGGER_LEVEL, 163 .handler = console_itr_cb, 164 }; 165 KEEP_PAGER(console_itr); 166 167 static TEE_Result init_console_itr(void) 168 { 169 itr_add(&console_itr); 170 itr_enable(&console_itr); 171 return TEE_SUCCESS; 172 } 173 driver_init(init_console_itr); 174 #endif 175