1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016-2020, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #include <arm.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/hfic.h> 11 #include <drivers/pl011.h> 12 #include <drivers/tzc400.h> 13 #include <initcall.h> 14 #include <keep.h> 15 #include <kernel/boot.h> 16 #include <kernel/interrupt.h> 17 #include <kernel/misc.h> 18 #include <kernel/notif.h> 19 #include <kernel/panic.h> 20 #include <kernel/spinlock.h> 21 #include <kernel/tee_time.h> 22 #include <mm/core_memprot.h> 23 #include <mm/core_mmu.h> 24 #include <platform_config.h> 25 #include <sm/psci.h> 26 #include <stdint.h> 27 #include <string.h> 28 #include <trace.h> 29 30 static struct pl011_data console_data __nex_bss; 31 32 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 33 #if defined(PLATFORM_FLAVOR_fvp) 34 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE); 35 #endif 36 #if defined(PLATFORM_FLAVOR_qemu_virt) 37 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE); 38 #endif 39 #ifdef DRAM0_BASE 40 register_ddr(DRAM0_BASE, DRAM0_SIZE); 41 #endif 42 #ifdef DRAM1_BASE 43 register_ddr(DRAM1_BASE, DRAM1_SIZE); 44 #endif 45 46 #ifdef CFG_GIC 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); 49 50 void boot_primary_init_intc(void) 51 { 52 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 53 } 54 55 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 56 void boot_secondary_init_intc(void) 57 { 58 gic_cpu_init(); 59 } 60 #endif 61 #endif /*CFG_GIC*/ 62 63 #ifdef CFG_CORE_HAFNIUM_INTC 64 void boot_primary_init_intc(void) 65 { 66 hfic_init(); 67 } 68 #endif 69 70 void console_init(void) 71 { 72 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 73 CONSOLE_BAUDRATE); 74 register_serial_console(&console_data.chip); 75 } 76 77 #if (defined(CFG_GIC) || defined(CFG_CORE_HAFNIUM_INTC)) && \ 78 defined(IT_CONSOLE_UART) && \ 79 !defined(CFG_NS_VIRTUALIZATION) && \ 80 !(defined(CFG_WITH_ARM_TRUSTED_FW) && defined(CFG_ARM_GICV2)) 81 /* 82 * This cannot be enabled with TF-A and GICv3 because TF-A then need to 83 * assign the interrupt number of the UART to OP-TEE (S-EL1). Currently 84 * there's no way of TF-A to know which interrupts that OP-TEE will serve. 85 * If TF-A doesn't assign the interrupt we're enabling below to OP-TEE it 86 * will hang in EL3 since the interrupt will just be delivered again and 87 * again. 88 */ 89 90 static void read_console(void) 91 { 92 struct serial_chip *cons = &console_data.chip; 93 94 if (!cons->ops->getchar || !cons->ops->have_rx_data) 95 return; 96 97 while (cons->ops->have_rx_data(cons)) { 98 int ch __maybe_unused = cons->ops->getchar(cons); 99 100 DMSG("got 0x%x", ch); 101 } 102 } 103 104 static enum itr_return console_itr_cb(struct itr_handler *hdl) 105 { 106 if (notif_async_is_started()) { 107 /* 108 * Asynchronous notifications are enabled, lets read from 109 * uart in the bottom half instead. 110 */ 111 interrupt_disable(hdl->chip, hdl->it); 112 notif_send_async(NOTIF_VALUE_DO_BOTTOM_HALF); 113 } else { 114 read_console(); 115 } 116 return ITRR_HANDLED; 117 } 118 119 static struct itr_handler console_itr = { 120 .it = IT_CONSOLE_UART, 121 .flags = ITRF_TRIGGER_LEVEL, 122 .handler = console_itr_cb, 123 }; 124 DECLARE_KEEP_PAGER(console_itr); 125 126 static void atomic_console_notif(struct notif_driver *ndrv __unused, 127 enum notif_event ev __maybe_unused) 128 { 129 DMSG("Asynchronous notifications started, event %d", (int)ev); 130 } 131 DECLARE_KEEP_PAGER(atomic_console_notif); 132 133 static void yielding_console_notif(struct notif_driver *ndrv __unused, 134 enum notif_event ev) 135 { 136 switch (ev) { 137 case NOTIF_EVENT_DO_BOTTOM_HALF: 138 read_console(); 139 interrupt_enable(console_itr.chip, console_itr.it); 140 break; 141 case NOTIF_EVENT_STOPPED: 142 DMSG("Asynchronous notifications stopped"); 143 interrupt_enable(console_itr.chip, console_itr.it); 144 break; 145 default: 146 EMSG("Unknown event %d", (int)ev); 147 } 148 } 149 150 struct notif_driver console_notif = { 151 .atomic_cb = atomic_console_notif, 152 .yielding_cb = yielding_console_notif, 153 }; 154 155 static TEE_Result init_console_itr(void) 156 { 157 TEE_Result res = TEE_ERROR_GENERIC; 158 159 res = interrupt_add_handler_with_chip(interrupt_get_main_chip(), 160 &console_itr); 161 if (res) 162 return res; 163 164 interrupt_enable(console_itr.chip, console_itr.it); 165 166 if (IS_ENABLED(CFG_CORE_ASYNC_NOTIF)) 167 notif_register_driver(&console_notif); 168 return TEE_SUCCESS; 169 } 170 driver_init(init_console_itr); 171 #endif 172 173 #ifdef CFG_TZC400 174 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 175 176 static TEE_Result init_tzc400(void) 177 { 178 void *va; 179 180 DMSG("Initializing TZC400"); 181 182 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC, TZC400_REG_SIZE); 183 if (!va) { 184 EMSG("TZC400 not mapped"); 185 panic(); 186 } 187 188 tzc_init((vaddr_t)va); 189 tzc_dump_state(); 190 191 return TEE_SUCCESS; 192 } 193 194 service_init(init_tzc400); 195 #endif /*CFG_TZC400*/ 196 197 #if defined(PLATFORM_FLAVOR_qemu_virt) 198 static void release_secondary_early_hpen(size_t pos) 199 { 200 struct mailbox { 201 uint64_t ep; 202 uint64_t hpen[]; 203 } *mailbox; 204 205 if (cpu_mmu_enabled()) 206 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC, 207 SECRAM_COHERENT_SIZE); 208 else 209 mailbox = (void *)SECRAM_BASE; 210 211 if (!mailbox) 212 panic(); 213 214 mailbox->ep = TEE_LOAD_ADDR; 215 dsb_ishst(); 216 mailbox->hpen[pos] = 1; 217 dsb_ishst(); 218 sev(); 219 } 220 221 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 222 { 223 size_t pos = get_core_pos_mpidr(core_id); 224 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 225 226 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 227 return PSCI_RET_INVALID_PARAMETERS; 228 229 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 230 231 if (core_is_released[pos]) { 232 EMSG("core %zu already released", pos); 233 return PSCI_RET_DENIED; 234 } 235 core_is_released[pos] = true; 236 237 boot_set_core_ns_entry(pos, entry, context_id); 238 release_secondary_early_hpen(pos); 239 240 return PSCI_RET_SUCCESS; 241 } 242 #endif /*PLATFORM_FLAVOR_qemu_virt*/ 243