1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <arm.h> 31 #include <console.h> 32 #include <drivers/gic.h> 33 #include <drivers/pl011.h> 34 #include <drivers/tzc400.h> 35 #include <initcall.h> 36 #include <keep.h> 37 #include <kernel/generic_boot.h> 38 #include <kernel/misc.h> 39 #include <kernel/panic.h> 40 #include <kernel/pm_stubs.h> 41 #include <kernel/tee_time.h> 42 #include <mm/core_memprot.h> 43 #include <mm/core_mmu.h> 44 #include <platform_config.h> 45 #include <sm/psci.h> 46 #include <stdint.h> 47 #include <string.h> 48 #include <tee/entry_fast.h> 49 #include <tee/entry_std.h> 50 #include <trace.h> 51 52 static void main_fiq(void); 53 54 static const struct thread_handlers handlers = { 55 .std_smc = tee_entry_std, 56 .fast_smc = tee_entry_fast, 57 .nintr = main_fiq, 58 #if defined(CFG_WITH_ARM_TRUSTED_FW) 59 .cpu_on = cpu_on_handler, 60 .cpu_off = pm_do_nothing, 61 .cpu_suspend = pm_do_nothing, 62 .cpu_resume = pm_do_nothing, 63 .system_off = pm_do_nothing, 64 .system_reset = pm_do_nothing, 65 #else 66 .cpu_on = pm_panic, 67 .cpu_off = pm_panic, 68 .cpu_suspend = pm_panic, 69 .cpu_resume = pm_panic, 70 .system_off = pm_panic, 71 .system_reset = pm_panic, 72 #endif 73 }; 74 75 static struct gic_data gic_data; 76 static struct pl011_data console_data; 77 78 #if defined(PLATFORM_FLAVOR_fvp) 79 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE); 80 #endif 81 #if defined(PLATFORM_FLAVOR_qemu_virt) 82 register_phys_mem(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE); 83 #endif 84 register_phys_mem(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 85 register_ddr(DRAM0_BASE, DRAM0_SIZE); 86 #ifdef DRAM1_BASE 87 register_ddr(DRAM1_BASE, DRAM1_SIZE); 88 #endif 89 90 const struct thread_handlers *generic_boot_get_handlers(void) 91 { 92 return &handlers; 93 } 94 95 #ifdef GIC_BASE 96 97 register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 98 register_phys_mem(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); 99 100 void main_init_gic(void) 101 { 102 vaddr_t gicc_base; 103 vaddr_t gicd_base; 104 105 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 106 MEM_AREA_IO_SEC); 107 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 108 MEM_AREA_IO_SEC); 109 if (!gicc_base || !gicd_base) 110 panic(); 111 112 #if defined(CFG_WITH_ARM_TRUSTED_FW) 113 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 114 gic_init_base_addr(&gic_data, gicc_base, gicd_base); 115 #else 116 /* Initialize GIC */ 117 gic_init(&gic_data, gicc_base, gicd_base); 118 #endif 119 itr_init(&gic_data.chip); 120 } 121 122 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 123 void main_secondary_init_gic(void) 124 { 125 gic_cpu_init(&gic_data); 126 } 127 #endif 128 129 #endif 130 131 static void main_fiq(void) 132 { 133 gic_it_handle(&gic_data); 134 } 135 136 void console_init(void) 137 { 138 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 139 CONSOLE_BAUDRATE); 140 register_serial_console(&console_data.chip); 141 } 142 143 #ifdef IT_CONSOLE_UART 144 static enum itr_return console_itr_cb(struct itr_handler *h __unused) 145 { 146 struct serial_chip *cons = &console_data.chip; 147 148 while (cons->ops->have_rx_data(cons)) { 149 int ch __maybe_unused = cons->ops->getchar(cons); 150 151 DMSG("cpu %zu: got 0x%x", get_core_pos(), ch); 152 } 153 return ITRR_HANDLED; 154 } 155 156 static struct itr_handler console_itr = { 157 .it = IT_CONSOLE_UART, 158 .flags = ITRF_TRIGGER_LEVEL, 159 .handler = console_itr_cb, 160 }; 161 KEEP_PAGER(console_itr); 162 163 static TEE_Result init_console_itr(void) 164 { 165 itr_add(&console_itr); 166 itr_enable(IT_CONSOLE_UART); 167 return TEE_SUCCESS; 168 } 169 driver_init(init_console_itr); 170 #endif 171 172 #ifdef CFG_TZC400 173 register_phys_mem(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 174 175 static TEE_Result init_tzc400(void) 176 { 177 void *va; 178 179 DMSG("Initializing TZC400"); 180 181 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC); 182 if (!va) { 183 EMSG("TZC400 not mapped"); 184 panic(); 185 } 186 187 tzc_init((vaddr_t)va); 188 tzc_dump_state(); 189 190 return TEE_SUCCESS; 191 } 192 193 service_init(init_tzc400); 194 #endif /*CFG_TZC400*/ 195 196 #if defined(PLATFORM_FLAVOR_qemu_virt) 197 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 198 { 199 size_t pos = get_core_pos_mpidr(core_id); 200 uint32_t *sec_entry_addrs = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC); 201 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 202 203 if (!sec_entry_addrs) 204 panic(); 205 206 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 207 return PSCI_RET_INVALID_PARAMETERS; 208 209 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 210 211 if (core_is_released[pos]) { 212 EMSG("core %zu already released", pos); 213 return PSCI_RET_DENIED; 214 } 215 core_is_released[pos] = true; 216 217 /* set NS entry addresses of core */ 218 generic_boot_set_core_ns_entry(pos, entry, context_id); 219 220 sec_entry_addrs[pos] = CFG_TEE_LOAD_ADDR; 221 dsb_ishst(); 222 sev(); 223 224 return PSCI_RET_SUCCESS; 225 } 226 #endif /*PLATFORM_FLAVOR_qemu_virt*/ 227