1 /* 2 * Copyright (c) 2016, Linaro Limited 3 * Copyright (c) 2014, STMicroelectronics International N.V. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <arm.h> 30 #include <console.h> 31 #include <drivers/gic.h> 32 #include <drivers/pl011.h> 33 #include <drivers/tzc400.h> 34 #include <initcall.h> 35 #include <keep.h> 36 #include <kernel/generic_boot.h> 37 #include <kernel/misc.h> 38 #include <kernel/panic.h> 39 #include <kernel/pm_stubs.h> 40 #include <kernel/tee_time.h> 41 #include <mm/core_memprot.h> 42 #include <mm/core_mmu.h> 43 #include <platform_config.h> 44 #include <sm/psci.h> 45 #include <stdint.h> 46 #include <string.h> 47 #include <tee/entry_fast.h> 48 #include <tee/entry_std.h> 49 #include <trace.h> 50 51 static void main_fiq(void); 52 53 static const struct thread_handlers handlers = { 54 .std_smc = tee_entry_std, 55 .fast_smc = tee_entry_fast, 56 .nintr = main_fiq, 57 #if defined(CFG_WITH_ARM_TRUSTED_FW) 58 .cpu_on = cpu_on_handler, 59 .cpu_off = pm_do_nothing, 60 .cpu_suspend = pm_do_nothing, 61 .cpu_resume = pm_do_nothing, 62 .system_off = pm_do_nothing, 63 .system_reset = pm_do_nothing, 64 #else 65 .cpu_on = pm_panic, 66 .cpu_off = pm_panic, 67 .cpu_suspend = pm_panic, 68 .cpu_resume = pm_panic, 69 .system_off = pm_panic, 70 .system_reset = pm_panic, 71 #endif 72 }; 73 74 static struct gic_data gic_data; 75 static struct pl011_data console_data; 76 77 #if defined(PLATFORM_FLAVOR_fvp) 78 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE); 79 #endif 80 #if defined(PLATFORM_FLAVOR_qemu_virt) 81 register_phys_mem(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE); 82 #endif 83 register_phys_mem(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 84 register_nsec_ddr(DRAM0_BASE, DRAM0_SIZE); 85 #ifdef DRAM1_BASE 86 register_nsec_ddr(DRAM1_BASE, DRAM1_SIZE); 87 #endif 88 89 const struct thread_handlers *generic_boot_get_handlers(void) 90 { 91 return &handlers; 92 } 93 94 #ifdef GIC_BASE 95 96 register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 97 register_phys_mem(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); 98 99 void main_init_gic(void) 100 { 101 vaddr_t gicc_base; 102 vaddr_t gicd_base; 103 104 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 105 MEM_AREA_IO_SEC); 106 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 107 MEM_AREA_IO_SEC); 108 if (!gicc_base || !gicd_base) 109 panic(); 110 111 #if defined(CFG_WITH_ARM_TRUSTED_FW) 112 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 113 gic_init_base_addr(&gic_data, gicc_base, gicd_base); 114 #else 115 /* Initialize GIC */ 116 gic_init(&gic_data, gicc_base, gicd_base); 117 #endif 118 itr_init(&gic_data.chip); 119 } 120 121 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 122 void main_secondary_init_gic(void) 123 { 124 gic_cpu_init(&gic_data); 125 } 126 #endif 127 128 #endif 129 130 static void main_fiq(void) 131 { 132 gic_it_handle(&gic_data); 133 } 134 135 void console_init(void) 136 { 137 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 138 CONSOLE_BAUDRATE); 139 register_serial_console(&console_data.chip); 140 } 141 142 #ifdef IT_CONSOLE_UART 143 static enum itr_return console_itr_cb(struct itr_handler *h __unused) 144 { 145 struct serial_chip *cons = &console_data.chip; 146 147 while (cons->ops->have_rx_data(cons)) { 148 int ch __maybe_unused = cons->ops->getchar(cons); 149 150 DMSG("cpu %zu: got 0x%x", get_core_pos(), ch); 151 } 152 return ITRR_HANDLED; 153 } 154 155 static struct itr_handler console_itr = { 156 .it = IT_CONSOLE_UART, 157 .flags = ITRF_TRIGGER_LEVEL, 158 .handler = console_itr_cb, 159 }; 160 KEEP_PAGER(console_itr); 161 162 static TEE_Result init_console_itr(void) 163 { 164 itr_add(&console_itr); 165 itr_enable(IT_CONSOLE_UART); 166 return TEE_SUCCESS; 167 } 168 driver_init(init_console_itr); 169 #endif 170 171 #ifdef CFG_TZC400 172 register_phys_mem(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 173 174 static TEE_Result init_tzc400(void) 175 { 176 void *va; 177 178 DMSG("Initializing TZC400"); 179 180 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC); 181 if (!va) { 182 EMSG("TZC400 not mapped"); 183 panic(); 184 } 185 186 tzc_init((vaddr_t)va); 187 tzc_dump_state(); 188 189 return TEE_SUCCESS; 190 } 191 192 service_init(init_tzc400); 193 #endif /*CFG_TZC400*/ 194 195 #if defined(PLATFORM_FLAVOR_qemu_virt) 196 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id __unused) 197 { 198 size_t pos = get_core_pos_mpidr(core_id); 199 uint32_t *sec_entry_addrs = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC); 200 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 201 202 if (!sec_entry_addrs) 203 panic(); 204 205 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 206 return PSCI_RET_INVALID_PARAMETERS; 207 208 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 209 210 if (core_is_released[pos]) { 211 EMSG("core %zu already released", pos); 212 return PSCI_RET_DENIED; 213 } 214 core_is_released[pos] = true; 215 216 /* set NS entry addresses of core */ 217 ns_entry_addrs[pos] = entry; 218 dsb_ishst(); 219 220 sec_entry_addrs[pos] = CFG_TEE_LOAD_ADDR; 221 dsb_ishst(); 222 sev(); 223 224 return PSCI_RET_SUCCESS; 225 } 226 #endif /*PLATFORM_FLAVOR_qemu_virt*/ 227