1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016-2023, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #include <arm.h> 8 #include <config.h> 9 #include <console.h> 10 #include <drivers/gic.h> 11 #include <drivers/hfic.h> 12 #include <drivers/pl011.h> 13 #include <drivers/tzc400.h> 14 #include <initcall.h> 15 #include <keep.h> 16 #include <kernel/boot.h> 17 #include <kernel/interrupt.h> 18 #include <kernel/misc.h> 19 #include <kernel/notif.h> 20 #include <kernel/panic.h> 21 #include <kernel/thread_spmc.h> 22 #include <kernel/timer.h> 23 #include <mm/core_memprot.h> 24 #include <mm/core_mmu.h> 25 #include <platform_config.h> 26 #include <sm/psci.h> 27 #include <stdint.h> 28 #include <trace.h> 29 30 static struct pl011_data console_data __nex_bss; 31 32 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 33 #if defined(PLATFORM_FLAVOR_fvp) 34 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE); 35 #endif 36 #if defined(PLATFORM_FLAVOR_qemu_virt) 37 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE); 38 #endif 39 #ifdef DRAM0_BASE 40 register_ddr(DRAM0_BASE, DRAM0_SIZE); 41 #endif 42 #ifdef DRAM1_BASE 43 register_ddr(DRAM1_BASE, DRAM1_SIZE); 44 #endif 45 46 #ifdef CFG_GIC 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 49 #ifdef GIC_REDIST_BASE 50 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_REDIST_BASE, GIC_REDIST_SIZE); 51 #endif 52 53 void boot_primary_init_intc(void) 54 { 55 #ifdef GIC_REDIST_BASE 56 gic_init_v3(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET, 57 GIC_REDIST_BASE); 58 #else 59 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 60 #endif 61 if (IS_ENABLED(CFG_CORE_SEL1_SPMC) && 62 IS_ENABLED(CFG_CORE_ASYNC_NOTIF)) { 63 size_t it = CFG_CORE_ASYNC_NOTIF_GIC_INTID; 64 65 if (it >= GIC_SGI_SEC_BASE && it <= GIC_SGI_SEC_MAX) 66 gic_init_donate_sgi_to_ns(it); 67 thread_spmc_set_async_notif_intid(it); 68 } 69 } 70 71 void boot_secondary_init_intc(void) 72 { 73 gic_init_per_cpu(); 74 } 75 #endif /*CFG_GIC*/ 76 77 #ifdef CFG_CORE_HAFNIUM_INTC 78 void boot_primary_init_intc(void) 79 { 80 hfic_init(); 81 } 82 #endif 83 84 void plat_console_init(void) 85 { 86 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 87 CONSOLE_BAUDRATE); 88 register_serial_console(&console_data.chip); 89 } 90 91 #if (defined(CFG_GIC) || defined(CFG_CORE_HAFNIUM_INTC)) && \ 92 defined(IT_CONSOLE_UART) && \ 93 !defined(CFG_NS_VIRTUALIZATION) && \ 94 !(defined(CFG_WITH_ARM_TRUSTED_FW) && defined(CFG_ARM_GICV2)) && \ 95 !defined(CFG_SEMIHOSTING_CONSOLE) && \ 96 !defined(CFG_FFA_CONSOLE) 97 /* 98 * This cannot be enabled with TF-A and GICv3 because TF-A then need to 99 * assign the interrupt number of the UART to OP-TEE (S-EL1). Currently 100 * there's no way of TF-A to know which interrupts that OP-TEE will serve. 101 * If TF-A doesn't assign the interrupt we're enabling below to OP-TEE it 102 * will hang in EL3 since the interrupt will just be delivered again and 103 * again. 104 */ 105 106 static void read_console(void) 107 { 108 struct serial_chip *cons = &console_data.chip; 109 110 if (!cons->ops->getchar || !cons->ops->have_rx_data) 111 return; 112 113 while (cons->ops->have_rx_data(cons)) { 114 int ch __maybe_unused = cons->ops->getchar(cons); 115 116 DMSG("got 0x%x", ch); 117 } 118 } 119 120 static enum itr_return console_itr_cb(struct itr_handler *hdl __unused) 121 { 122 if (notif_async_is_started()) { 123 /* 124 * Asynchronous notifications are enabled, lets read from 125 * uart in the bottom half instead. 126 */ 127 console_data.chip.ops->rx_intr_disable(&console_data.chip); 128 notif_send_async(NOTIF_VALUE_DO_BOTTOM_HALF); 129 } else { 130 read_console(); 131 } 132 return ITRR_HANDLED; 133 } 134 135 static struct itr_handler console_itr = { 136 .it = IT_CONSOLE_UART, 137 .flags = ITRF_TRIGGER_LEVEL, 138 .handler = console_itr_cb, 139 }; 140 DECLARE_KEEP_PAGER(console_itr); 141 142 static void atomic_console_notif(struct notif_driver *ndrv __unused, 143 enum notif_event ev __maybe_unused) 144 { 145 DMSG("Asynchronous notifications started, event %d", (int)ev); 146 } 147 DECLARE_KEEP_PAGER(atomic_console_notif); 148 149 static void yielding_console_notif(struct notif_driver *ndrv __unused, 150 enum notif_event ev) 151 { 152 switch (ev) { 153 case NOTIF_EVENT_DO_BOTTOM_HALF: 154 read_console(); 155 console_data.chip.ops->rx_intr_enable(&console_data.chip); 156 break; 157 case NOTIF_EVENT_STOPPED: 158 DMSG("Asynchronous notifications stopped"); 159 console_data.chip.ops->rx_intr_enable(&console_data.chip); 160 break; 161 default: 162 EMSG("Unknown event %d", (int)ev); 163 } 164 } 165 166 struct notif_driver console_notif = { 167 .atomic_cb = atomic_console_notif, 168 .yielding_cb = yielding_console_notif, 169 }; 170 171 static TEE_Result init_console_itr(void) 172 { 173 TEE_Result res = TEE_ERROR_GENERIC; 174 bool have_itr_ctrl = console_data.chip.ops->rx_intr_enable && 175 console_data.chip.ops->rx_intr_disable; 176 177 res = interrupt_add_handler_with_chip(interrupt_get_main_chip(), 178 &console_itr); 179 if (res) 180 return res; 181 182 interrupt_enable(console_itr.chip, console_itr.it); 183 184 if (IS_ENABLED(CFG_CORE_ASYNC_NOTIF) && have_itr_ctrl) 185 notif_register_driver(&console_notif); 186 return TEE_SUCCESS; 187 } 188 driver_init(init_console_itr); 189 #endif 190 191 #ifdef CFG_TZC400 192 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 193 194 static TEE_Result init_tzc400(void) 195 { 196 void *va; 197 198 DMSG("Initializing TZC400"); 199 200 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC, TZC400_REG_SIZE); 201 if (!va) { 202 EMSG("TZC400 not mapped"); 203 panic(); 204 } 205 206 tzc_init((vaddr_t)va); 207 tzc_dump_state(); 208 209 return TEE_SUCCESS; 210 } 211 212 service_init(init_tzc400); 213 #endif /*CFG_TZC400*/ 214 215 #if defined(PLATFORM_FLAVOR_qemu_virt) 216 static void release_secondary_early_hpen(size_t pos) 217 { 218 struct mailbox { 219 uint64_t ep; 220 uint64_t hpen[]; 221 } *mailbox; 222 223 if (cpu_mmu_enabled()) 224 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC, 225 SECRAM_COHERENT_SIZE); 226 else 227 mailbox = (void *)SECRAM_BASE; 228 229 if (!mailbox) 230 panic(); 231 232 mailbox->ep = TEE_LOAD_ADDR; 233 dsb_ishst(); 234 mailbox->hpen[pos] = 1; 235 dsb_ishst(); 236 sev(); 237 } 238 239 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 240 { 241 size_t pos = get_core_pos_mpidr(core_id); 242 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 243 244 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 245 return PSCI_RET_INVALID_PARAMETERS; 246 247 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 248 249 if (core_is_released[pos]) { 250 EMSG("core %zu already released", pos); 251 return PSCI_RET_DENIED; 252 } 253 core_is_released[pos] = true; 254 255 boot_set_core_ns_entry(pos, entry, context_id); 256 release_secondary_early_hpen(pos); 257 258 return PSCI_RET_SUCCESS; 259 } 260 #endif /*PLATFORM_FLAVOR_qemu_virt*/ 261 262 #if defined(CFG_CALLOUT) && defined(IT_SEC_PHY_TIMER) && \ 263 !defined(CFG_CORE_SEL2_SPMC) 264 static TEE_Result init_callout_service(void) 265 { 266 timer_init_callout_service(interrupt_get_main_chip(), IT_SEC_PHY_TIMER); 267 268 return TEE_SUCCESS; 269 } 270 271 nex_early_init(init_callout_service); 272 #endif 273