1 /* 2 * Copyright (c) 2016, Linaro Limited 3 * Copyright (c) 2014, STMicroelectronics International N.V. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <platform_config.h> 30 31 #include <stdint.h> 32 #include <string.h> 33 34 #include <drivers/gic.h> 35 #include <drivers/pl011.h> 36 37 #include <arm.h> 38 #include <kernel/generic_boot.h> 39 #include <kernel/pm_stubs.h> 40 #include <trace.h> 41 #include <kernel/misc.h> 42 #include <kernel/panic.h> 43 #include <kernel/tee_time.h> 44 #include <tee/entry_fast.h> 45 #include <tee/entry_std.h> 46 #include <mm/core_memprot.h> 47 #include <mm/core_mmu.h> 48 #include <console.h> 49 #include <keep.h> 50 #include <initcall.h> 51 52 static void main_fiq(void); 53 54 static const struct thread_handlers handlers = { 55 .std_smc = tee_entry_std, 56 .fast_smc = tee_entry_fast, 57 .fiq = main_fiq, 58 #if defined(CFG_WITH_ARM_TRUSTED_FW) 59 .cpu_on = cpu_on_handler, 60 .cpu_off = pm_do_nothing, 61 .cpu_suspend = pm_do_nothing, 62 .cpu_resume = pm_do_nothing, 63 .system_off = pm_do_nothing, 64 .system_reset = pm_do_nothing, 65 #else 66 .cpu_on = pm_panic, 67 .cpu_off = pm_panic, 68 .cpu_suspend = pm_panic, 69 .cpu_resume = pm_panic, 70 .system_off = pm_panic, 71 .system_reset = pm_panic, 72 #endif 73 }; 74 75 static struct gic_data gic_data; 76 77 register_phys_mem(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 78 79 const struct thread_handlers *generic_boot_get_handlers(void) 80 { 81 return &handlers; 82 } 83 84 #ifdef GIC_BASE 85 86 register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 87 register_phys_mem(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); 88 89 void main_init_gic(void) 90 { 91 vaddr_t gicc_base; 92 vaddr_t gicd_base; 93 94 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 95 MEM_AREA_IO_SEC); 96 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 97 MEM_AREA_IO_SEC); 98 if (!gicc_base || !gicd_base) 99 panic(); 100 101 #if defined(PLATFORM_FLAVOR_fvp) || defined(PLATFORM_FLAVOR_juno) || \ 102 defined(PLATFORM_FLAVOR_qemu_armv8a) 103 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 104 gic_init_base_addr(&gic_data, gicc_base, gicd_base); 105 #else 106 /* Initialize GIC */ 107 gic_init(&gic_data, gicc_base, gicd_base); 108 #endif 109 itr_init(&gic_data.chip); 110 } 111 #endif 112 113 static void main_fiq(void) 114 { 115 gic_it_handle(&gic_data); 116 } 117 118 static vaddr_t console_base(void) 119 { 120 static void *va; 121 122 if (cpu_mmu_enabled()) { 123 if (!va) 124 va = phys_to_virt(CONSOLE_UART_BASE, MEM_AREA_IO_SEC); 125 return (vaddr_t)va; 126 } 127 return CONSOLE_UART_BASE; 128 } 129 130 void console_init(void) 131 { 132 pl011_init(console_base(), CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE); 133 } 134 135 void console_putc(int ch) 136 { 137 vaddr_t base = console_base(); 138 139 if (ch == '\n') 140 pl011_putc('\r', base); 141 pl011_putc(ch, base); 142 } 143 144 void console_flush(void) 145 { 146 pl011_flush(console_base()); 147 } 148 149 #ifdef IT_CONSOLE_UART 150 static enum itr_return console_itr_cb(struct itr_handler *h __unused) 151 { 152 paddr_t uart_base = console_base(); 153 154 while (pl011_have_rx_data(uart_base)) { 155 int ch __maybe_unused = pl011_getchar(uart_base); 156 157 DMSG("cpu %zu: got 0x%x", get_core_pos(), ch); 158 } 159 return ITRR_HANDLED; 160 } 161 162 static struct itr_handler console_itr = { 163 .it = IT_CONSOLE_UART, 164 .flags = ITRF_TRIGGER_LEVEL, 165 .handler = console_itr_cb, 166 }; 167 KEEP_PAGER(console_itr); 168 169 static TEE_Result init_console_itr(void) 170 { 171 itr_add(&console_itr); 172 itr_enable(&console_itr); 173 return TEE_SUCCESS; 174 } 175 driver_init(init_console_itr); 176 #endif 177