1 /* 2 * Copyright (c) 2016, Linaro Limited 3 * Copyright (c) 2014, STMicroelectronics International N.V. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <platform_config.h> 30 31 #include <stdint.h> 32 #include <string.h> 33 34 #include <drivers/gic.h> 35 #include <drivers/pl011.h> 36 #include <drivers/tzc400.h> 37 38 #include <arm.h> 39 #include <kernel/generic_boot.h> 40 #include <kernel/pm_stubs.h> 41 #include <trace.h> 42 #include <kernel/misc.h> 43 #include <kernel/panic.h> 44 #include <kernel/tee_time.h> 45 #include <tee/entry_fast.h> 46 #include <tee/entry_std.h> 47 #include <mm/core_memprot.h> 48 #include <mm/core_mmu.h> 49 #include <console.h> 50 #include <keep.h> 51 #include <initcall.h> 52 53 static void main_fiq(void); 54 55 static const struct thread_handlers handlers = { 56 .std_smc = tee_entry_std, 57 .fast_smc = tee_entry_fast, 58 .fiq = main_fiq, 59 #if defined(CFG_WITH_ARM_TRUSTED_FW) 60 .cpu_on = cpu_on_handler, 61 .cpu_off = pm_do_nothing, 62 .cpu_suspend = pm_do_nothing, 63 .cpu_resume = pm_do_nothing, 64 .system_off = pm_do_nothing, 65 .system_reset = pm_do_nothing, 66 #else 67 .cpu_on = pm_panic, 68 .cpu_off = pm_panic, 69 .cpu_suspend = pm_panic, 70 .cpu_resume = pm_panic, 71 .system_off = pm_panic, 72 .system_reset = pm_panic, 73 #endif 74 }; 75 76 static struct gic_data gic_data; 77 78 register_phys_mem(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 79 80 const struct thread_handlers *generic_boot_get_handlers(void) 81 { 82 return &handlers; 83 } 84 85 #ifdef GIC_BASE 86 87 register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 88 register_phys_mem(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); 89 90 void main_init_gic(void) 91 { 92 vaddr_t gicc_base; 93 vaddr_t gicd_base; 94 95 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 96 MEM_AREA_IO_SEC); 97 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 98 MEM_AREA_IO_SEC); 99 if (!gicc_base || !gicd_base) 100 panic(); 101 102 #if defined(PLATFORM_FLAVOR_fvp) || defined(PLATFORM_FLAVOR_juno) || \ 103 defined(PLATFORM_FLAVOR_qemu_armv8a) 104 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 105 gic_init_base_addr(&gic_data, gicc_base, gicd_base); 106 #else 107 /* Initialize GIC */ 108 gic_init(&gic_data, gicc_base, gicd_base); 109 #endif 110 itr_init(&gic_data.chip); 111 } 112 #endif 113 114 static void main_fiq(void) 115 { 116 gic_it_handle(&gic_data); 117 } 118 119 static vaddr_t console_base(void) 120 { 121 static void *va; 122 123 if (cpu_mmu_enabled()) { 124 if (!va) 125 va = phys_to_virt(CONSOLE_UART_BASE, MEM_AREA_IO_SEC); 126 return (vaddr_t)va; 127 } 128 return CONSOLE_UART_BASE; 129 } 130 131 void console_init(void) 132 { 133 pl011_init(console_base(), CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE); 134 } 135 136 void console_putc(int ch) 137 { 138 vaddr_t base = console_base(); 139 140 if (ch == '\n') 141 pl011_putc('\r', base); 142 pl011_putc(ch, base); 143 } 144 145 void console_flush(void) 146 { 147 pl011_flush(console_base()); 148 } 149 150 #ifdef IT_CONSOLE_UART 151 static enum itr_return console_itr_cb(struct itr_handler *h __unused) 152 { 153 paddr_t uart_base = console_base(); 154 155 while (pl011_have_rx_data(uart_base)) { 156 int ch __maybe_unused = pl011_getchar(uart_base); 157 158 DMSG("cpu %zu: got 0x%x", get_core_pos(), ch); 159 } 160 return ITRR_HANDLED; 161 } 162 163 static struct itr_handler console_itr = { 164 .it = IT_CONSOLE_UART, 165 .flags = ITRF_TRIGGER_LEVEL, 166 .handler = console_itr_cb, 167 }; 168 KEEP_PAGER(console_itr); 169 170 static TEE_Result init_console_itr(void) 171 { 172 itr_add(&console_itr); 173 itr_enable(&console_itr); 174 return TEE_SUCCESS; 175 } 176 driver_init(init_console_itr); 177 #endif 178 179 #ifdef CFG_TZC400 180 register_phys_mem(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 181 182 static TEE_Result init_tzc400(void) 183 { 184 void *va; 185 186 DMSG("Initializing TZC400"); 187 188 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC); 189 if (!va) { 190 EMSG("TZC400 not mapped"); 191 panic(); 192 } 193 194 tzc_init((vaddr_t)va); 195 tzc_dump_state(); 196 197 return TEE_SUCCESS; 198 } 199 200 service_init(init_tzc400); 201 #endif /*CFG_TZC400*/ 202