1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #include <arm.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/pl011.h> 11 #include <drivers/tzc400.h> 12 #include <initcall.h> 13 #include <keep.h> 14 #include <kernel/generic_boot.h> 15 #include <kernel/misc.h> 16 #include <kernel/panic.h> 17 #include <kernel/pm_stubs.h> 18 #include <kernel/tee_time.h> 19 #include <mm/core_memprot.h> 20 #include <mm/core_mmu.h> 21 #include <platform_config.h> 22 #include <sm/psci.h> 23 #include <stdint.h> 24 #include <string.h> 25 #include <tee/entry_fast.h> 26 #include <tee/entry_std.h> 27 #include <trace.h> 28 29 static void main_fiq(void); 30 31 static const struct thread_handlers handlers = { 32 .std_smc = tee_entry_std, 33 .fast_smc = tee_entry_fast, 34 .nintr = main_fiq, 35 #if defined(CFG_WITH_ARM_TRUSTED_FW) 36 .cpu_on = cpu_on_handler, 37 .cpu_off = pm_do_nothing, 38 .cpu_suspend = pm_do_nothing, 39 .cpu_resume = pm_do_nothing, 40 .system_off = pm_do_nothing, 41 .system_reset = pm_do_nothing, 42 #else 43 .cpu_on = pm_panic, 44 .cpu_off = pm_panic, 45 .cpu_suspend = pm_panic, 46 .cpu_resume = pm_panic, 47 .system_off = pm_panic, 48 .system_reset = pm_panic, 49 #endif 50 }; 51 52 static struct gic_data gic_data __nex_bss; 53 static struct pl011_data console_data __nex_bss; 54 55 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 56 #if defined(PLATFORM_FLAVOR_fvp) 57 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE); 58 #endif 59 #if defined(PLATFORM_FLAVOR_qemu_virt) 60 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE); 61 #endif 62 #ifdef DRAM0_BASE 63 register_ddr(DRAM0_BASE, DRAM0_SIZE); 64 #endif 65 #ifdef DRAM1_BASE 66 register_ddr(DRAM1_BASE, DRAM1_SIZE); 67 #endif 68 69 const struct thread_handlers *generic_boot_get_handlers(void) 70 { 71 return &handlers; 72 } 73 74 #ifdef GIC_BASE 75 76 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 77 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); 78 79 void main_init_gic(void) 80 { 81 vaddr_t gicc_base; 82 vaddr_t gicd_base; 83 84 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 85 MEM_AREA_IO_SEC); 86 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 87 MEM_AREA_IO_SEC); 88 if (!gicc_base || !gicd_base) 89 panic(); 90 91 #if defined(CFG_WITH_ARM_TRUSTED_FW) 92 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 93 gic_init_base_addr(&gic_data, gicc_base, gicd_base); 94 #else 95 /* Initialize GIC */ 96 gic_init(&gic_data, gicc_base, gicd_base); 97 #endif 98 itr_init(&gic_data.chip); 99 } 100 101 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 102 void main_secondary_init_gic(void) 103 { 104 gic_cpu_init(&gic_data); 105 } 106 #endif 107 108 #endif 109 110 static void main_fiq(void) 111 { 112 gic_it_handle(&gic_data); 113 } 114 115 void console_init(void) 116 { 117 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 118 CONSOLE_BAUDRATE); 119 register_serial_console(&console_data.chip); 120 } 121 122 #if defined(IT_CONSOLE_UART) && \ 123 !(defined(CFG_WITH_ARM_TRUSTED_FW) && defined(CFG_ARM_GICV3)) 124 /* 125 * This cannot be enabled with TF-A and GICv3 because TF-A then need to 126 * assign the interrupt number of the UART to OP-TEE (S-EL1). Currently 127 * there's no way of TF-A to know which interrupts that OP-TEE will serve. 128 * If TF-A doesn't assign the interrupt we're enabling below to OP-TEE it 129 * will hang in EL3 since the interrupt will just be delivered again and 130 * again. 131 */ 132 static enum itr_return console_itr_cb(struct itr_handler *h __unused) 133 { 134 struct serial_chip *cons = &console_data.chip; 135 136 while (cons->ops->have_rx_data(cons)) { 137 int ch __maybe_unused = cons->ops->getchar(cons); 138 139 DMSG("cpu %zu: got 0x%x", get_core_pos(), ch); 140 } 141 return ITRR_HANDLED; 142 } 143 144 static struct itr_handler console_itr = { 145 .it = IT_CONSOLE_UART, 146 .flags = ITRF_TRIGGER_LEVEL, 147 .handler = console_itr_cb, 148 }; 149 KEEP_PAGER(console_itr); 150 151 static TEE_Result init_console_itr(void) 152 { 153 itr_add(&console_itr); 154 itr_enable(IT_CONSOLE_UART); 155 return TEE_SUCCESS; 156 } 157 driver_init(init_console_itr); 158 #endif 159 160 #ifdef CFG_TZC400 161 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 162 163 static TEE_Result init_tzc400(void) 164 { 165 void *va; 166 167 DMSG("Initializing TZC400"); 168 169 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC); 170 if (!va) { 171 EMSG("TZC400 not mapped"); 172 panic(); 173 } 174 175 tzc_init((vaddr_t)va); 176 tzc_dump_state(); 177 178 return TEE_SUCCESS; 179 } 180 181 service_init(init_tzc400); 182 #endif /*CFG_TZC400*/ 183 184 #if defined(PLATFORM_FLAVOR_qemu_virt) 185 static void release_secondary_early_hpen(size_t pos) 186 { 187 struct mailbox { 188 uint64_t ep; 189 uint64_t hpen[]; 190 } *mailbox; 191 192 if (cpu_mmu_enabled()) 193 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC); 194 else 195 mailbox = (void *)SECRAM_BASE; 196 197 if (!mailbox) 198 panic(); 199 200 mailbox->ep = TEE_LOAD_ADDR; 201 dsb_ishst(); 202 mailbox->hpen[pos] = 1; 203 dsb_ishst(); 204 sev(); 205 } 206 207 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 208 { 209 size_t pos = get_core_pos_mpidr(core_id); 210 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 211 212 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 213 return PSCI_RET_INVALID_PARAMETERS; 214 215 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 216 217 if (core_is_released[pos]) { 218 EMSG("core %zu already released", pos); 219 return PSCI_RET_DENIED; 220 } 221 core_is_released[pos] = true; 222 223 generic_boot_set_core_ns_entry(pos, entry, context_id); 224 release_secondary_early_hpen(pos); 225 226 return PSCI_RET_SUCCESS; 227 } 228 #endif /*PLATFORM_FLAVOR_qemu_virt*/ 229