1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016-2023, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #include <arm.h> 8 #include <config.h> 9 #include <console.h> 10 #include <drivers/gic.h> 11 #include <drivers/hfic.h> 12 #include <drivers/pl011.h> 13 #include <drivers/tzc400.h> 14 #include <initcall.h> 15 #include <keep.h> 16 #include <kernel/boot.h> 17 #include <kernel/interrupt.h> 18 #include <kernel/misc.h> 19 #include <kernel/notif.h> 20 #include <kernel/panic.h> 21 #include <kernel/spinlock.h> 22 #include <kernel/tee_time.h> 23 #include <kernel/thread_spmc.h> 24 #include <mm/core_memprot.h> 25 #include <mm/core_mmu.h> 26 #include <platform_config.h> 27 #include <sm/psci.h> 28 #include <stdint.h> 29 #include <string.h> 30 #include <trace.h> 31 32 static struct pl011_data console_data __nex_bss; 33 34 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 35 #if defined(PLATFORM_FLAVOR_fvp) 36 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE); 37 #endif 38 #if defined(PLATFORM_FLAVOR_qemu_virt) 39 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE); 40 #endif 41 #ifdef DRAM0_BASE 42 register_ddr(DRAM0_BASE, DRAM0_SIZE); 43 #endif 44 #ifdef DRAM1_BASE 45 register_ddr(DRAM1_BASE, DRAM1_SIZE); 46 #endif 47 48 #ifdef CFG_GIC 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE); 50 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 51 #ifdef GIC_REDIST_BASE 52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_REDIST_BASE, GIC_REDIST_SIZE); 53 #endif 54 55 void boot_primary_init_intc(void) 56 { 57 #ifdef GIC_REDIST_BASE 58 gic_init_v3(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET, 59 GIC_REDIST_BASE); 60 #else 61 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 62 #endif 63 if (IS_ENABLED(CFG_CORE_SEL1_SPMC) && 64 IS_ENABLED(CFG_CORE_ASYNC_NOTIF)) { 65 gic_init_donate_sgi_to_ns(GIC_SGI_SEC_BASE); 66 thread_spmc_set_async_notif_intid(GIC_SGI_SEC_BASE); 67 } 68 } 69 70 void boot_secondary_init_intc(void) 71 { 72 gic_init_per_cpu(); 73 } 74 #endif /*CFG_GIC*/ 75 76 #ifdef CFG_CORE_HAFNIUM_INTC 77 void boot_primary_init_intc(void) 78 { 79 hfic_init(); 80 } 81 #endif 82 83 void console_init(void) 84 { 85 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 86 CONSOLE_BAUDRATE); 87 register_serial_console(&console_data.chip); 88 } 89 90 #if (defined(CFG_GIC) || defined(CFG_CORE_HAFNIUM_INTC)) && \ 91 defined(IT_CONSOLE_UART) && \ 92 !defined(CFG_NS_VIRTUALIZATION) && \ 93 !(defined(CFG_WITH_ARM_TRUSTED_FW) && defined(CFG_ARM_GICV2)) 94 /* 95 * This cannot be enabled with TF-A and GICv3 because TF-A then need to 96 * assign the interrupt number of the UART to OP-TEE (S-EL1). Currently 97 * there's no way of TF-A to know which interrupts that OP-TEE will serve. 98 * If TF-A doesn't assign the interrupt we're enabling below to OP-TEE it 99 * will hang in EL3 since the interrupt will just be delivered again and 100 * again. 101 */ 102 103 static void read_console(void) 104 { 105 struct serial_chip *cons = &console_data.chip; 106 107 if (!cons->ops->getchar || !cons->ops->have_rx_data) 108 return; 109 110 while (cons->ops->have_rx_data(cons)) { 111 int ch __maybe_unused = cons->ops->getchar(cons); 112 113 DMSG("got 0x%x", ch); 114 } 115 } 116 117 static enum itr_return console_itr_cb(struct itr_handler *hdl) 118 { 119 if (notif_async_is_started()) { 120 /* 121 * Asynchronous notifications are enabled, lets read from 122 * uart in the bottom half instead. 123 */ 124 interrupt_disable(hdl->chip, hdl->it); 125 notif_send_async(NOTIF_VALUE_DO_BOTTOM_HALF); 126 } else { 127 read_console(); 128 } 129 return ITRR_HANDLED; 130 } 131 132 static struct itr_handler console_itr = { 133 .it = IT_CONSOLE_UART, 134 .flags = ITRF_TRIGGER_LEVEL, 135 .handler = console_itr_cb, 136 }; 137 DECLARE_KEEP_PAGER(console_itr); 138 139 static void atomic_console_notif(struct notif_driver *ndrv __unused, 140 enum notif_event ev __maybe_unused) 141 { 142 DMSG("Asynchronous notifications started, event %d", (int)ev); 143 } 144 DECLARE_KEEP_PAGER(atomic_console_notif); 145 146 static void yielding_console_notif(struct notif_driver *ndrv __unused, 147 enum notif_event ev) 148 { 149 switch (ev) { 150 case NOTIF_EVENT_DO_BOTTOM_HALF: 151 read_console(); 152 interrupt_enable(console_itr.chip, console_itr.it); 153 break; 154 case NOTIF_EVENT_STOPPED: 155 DMSG("Asynchronous notifications stopped"); 156 interrupt_enable(console_itr.chip, console_itr.it); 157 break; 158 default: 159 EMSG("Unknown event %d", (int)ev); 160 } 161 } 162 163 struct notif_driver console_notif = { 164 .atomic_cb = atomic_console_notif, 165 .yielding_cb = yielding_console_notif, 166 }; 167 168 static TEE_Result init_console_itr(void) 169 { 170 TEE_Result res = TEE_ERROR_GENERIC; 171 172 res = interrupt_add_handler_with_chip(interrupt_get_main_chip(), 173 &console_itr); 174 if (res) 175 return res; 176 177 interrupt_enable(console_itr.chip, console_itr.it); 178 179 if (IS_ENABLED(CFG_CORE_ASYNC_NOTIF)) 180 notif_register_driver(&console_notif); 181 return TEE_SUCCESS; 182 } 183 driver_init(init_console_itr); 184 #endif 185 186 #ifdef CFG_TZC400 187 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 188 189 static TEE_Result init_tzc400(void) 190 { 191 void *va; 192 193 DMSG("Initializing TZC400"); 194 195 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC, TZC400_REG_SIZE); 196 if (!va) { 197 EMSG("TZC400 not mapped"); 198 panic(); 199 } 200 201 tzc_init((vaddr_t)va); 202 tzc_dump_state(); 203 204 return TEE_SUCCESS; 205 } 206 207 service_init(init_tzc400); 208 #endif /*CFG_TZC400*/ 209 210 #if defined(PLATFORM_FLAVOR_qemu_virt) 211 static void release_secondary_early_hpen(size_t pos) 212 { 213 struct mailbox { 214 uint64_t ep; 215 uint64_t hpen[]; 216 } *mailbox; 217 218 if (cpu_mmu_enabled()) 219 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC, 220 SECRAM_COHERENT_SIZE); 221 else 222 mailbox = (void *)SECRAM_BASE; 223 224 if (!mailbox) 225 panic(); 226 227 mailbox->ep = TEE_LOAD_ADDR; 228 dsb_ishst(); 229 mailbox->hpen[pos] = 1; 230 dsb_ishst(); 231 sev(); 232 } 233 234 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 235 { 236 size_t pos = get_core_pos_mpidr(core_id); 237 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 238 239 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 240 return PSCI_RET_INVALID_PARAMETERS; 241 242 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 243 244 if (core_is_released[pos]) { 245 EMSG("core %zu already released", pos); 246 return PSCI_RET_DENIED; 247 } 248 core_is_released[pos] = true; 249 250 boot_set_core_ns_entry(pos, entry, context_id); 251 release_secondary_early_hpen(pos); 252 253 return PSCI_RET_SUCCESS; 254 } 255 #endif /*PLATFORM_FLAVOR_qemu_virt*/ 256