1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016-2020, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #include <arm.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/hfic.h> 11 #include <drivers/pl011.h> 12 #include <drivers/tzc400.h> 13 #include <initcall.h> 14 #include <keep.h> 15 #include <kernel/boot.h> 16 #include <kernel/interrupt.h> 17 #include <kernel/misc.h> 18 #include <kernel/notif.h> 19 #include <kernel/panic.h> 20 #include <kernel/spinlock.h> 21 #include <kernel/tee_time.h> 22 #include <mm/core_memprot.h> 23 #include <mm/core_mmu.h> 24 #include <platform_config.h> 25 #include <sm/psci.h> 26 #include <stdint.h> 27 #include <string.h> 28 #include <trace.h> 29 30 static struct gic_data gic_data __maybe_unused __nex_bss; 31 static struct hfic_data hfic_data __maybe_unused __nex_bss; 32 static struct pl011_data console_data __nex_bss; 33 34 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 35 #if defined(PLATFORM_FLAVOR_fvp) 36 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE); 37 #endif 38 #if defined(PLATFORM_FLAVOR_qemu_virt) 39 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE); 40 #endif 41 #ifdef DRAM0_BASE 42 register_ddr(DRAM0_BASE, DRAM0_SIZE); 43 #endif 44 #ifdef DRAM1_BASE 45 register_ddr(DRAM1_BASE, DRAM1_SIZE); 46 #endif 47 48 #ifdef CFG_GIC 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 50 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); 51 52 void main_init_gic(void) 53 { 54 #if defined(CFG_WITH_ARM_TRUSTED_FW) 55 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 56 gic_init_base_addr(&gic_data, GIC_BASE + GICC_OFFSET, 57 GIC_BASE + GICD_OFFSET); 58 #else 59 gic_init(&gic_data, GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 60 #endif 61 itr_init(&gic_data.chip); 62 } 63 64 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 65 void main_secondary_init_gic(void) 66 { 67 gic_cpu_init(&gic_data); 68 } 69 #endif 70 71 void itr_core_handler(void) 72 { 73 gic_it_handle(&gic_data); 74 } 75 #endif /*CFG_GIC*/ 76 77 #ifdef CFG_CORE_HAFNIUM_INTC 78 void main_init_gic(void) 79 { 80 hfic_init(&hfic_data); 81 itr_init(&hfic_data.chip); 82 } 83 84 void itr_core_handler(void) 85 { 86 hfic_it_handle(&hfic_data); 87 } 88 #endif 89 90 void console_init(void) 91 { 92 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 93 CONSOLE_BAUDRATE); 94 register_serial_console(&console_data.chip); 95 } 96 97 #if (defined(CFG_GIC) || defined(CFG_CORE_HAFNIUM_INTC)) && \ 98 defined(IT_CONSOLE_UART) && \ 99 !defined(CFG_NS_VIRTUALIZATION) && \ 100 !(defined(CFG_WITH_ARM_TRUSTED_FW) && defined(CFG_ARM_GICV2)) 101 /* 102 * This cannot be enabled with TF-A and GICv3 because TF-A then need to 103 * assign the interrupt number of the UART to OP-TEE (S-EL1). Currently 104 * there's no way of TF-A to know which interrupts that OP-TEE will serve. 105 * If TF-A doesn't assign the interrupt we're enabling below to OP-TEE it 106 * will hang in EL3 since the interrupt will just be delivered again and 107 * again. 108 */ 109 110 static void read_console(void) 111 { 112 struct serial_chip *cons = &console_data.chip; 113 114 if (!cons->ops->getchar || !cons->ops->have_rx_data) 115 return; 116 117 while (cons->ops->have_rx_data(cons)) { 118 int ch __maybe_unused = cons->ops->getchar(cons); 119 120 DMSG("got 0x%x", ch); 121 } 122 } 123 124 static enum itr_return console_itr_cb(struct itr_handler *h __maybe_unused) 125 { 126 if (notif_async_is_started()) { 127 /* 128 * Asynchronous notifications are enabled, lets read from 129 * uart in the bottom half instead. 130 */ 131 itr_disable(IT_CONSOLE_UART); 132 notif_send_async(NOTIF_VALUE_DO_BOTTOM_HALF); 133 } else { 134 read_console(); 135 } 136 return ITRR_HANDLED; 137 } 138 139 static struct itr_handler console_itr = { 140 .it = IT_CONSOLE_UART, 141 .flags = ITRF_TRIGGER_LEVEL, 142 .handler = console_itr_cb, 143 }; 144 DECLARE_KEEP_PAGER(console_itr); 145 146 static void atomic_console_notif(struct notif_driver *ndrv __unused, 147 enum notif_event ev __maybe_unused) 148 { 149 DMSG("Asynchronous notifications started, event %d", (int)ev); 150 } 151 DECLARE_KEEP_PAGER(atomic_console_notif); 152 153 static void yielding_console_notif(struct notif_driver *ndrv __unused, 154 enum notif_event ev) 155 { 156 switch (ev) { 157 case NOTIF_EVENT_DO_BOTTOM_HALF: 158 read_console(); 159 itr_enable(IT_CONSOLE_UART); 160 break; 161 case NOTIF_EVENT_STOPPED: 162 DMSG("Asynchronous notifications stopped"); 163 itr_enable(IT_CONSOLE_UART); 164 break; 165 default: 166 EMSG("Unknown event %d", (int)ev); 167 } 168 } 169 170 struct notif_driver console_notif = { 171 .atomic_cb = atomic_console_notif, 172 .yielding_cb = yielding_console_notif, 173 }; 174 175 static TEE_Result init_console_itr(void) 176 { 177 itr_add(&console_itr); 178 itr_enable(IT_CONSOLE_UART); 179 if (IS_ENABLED(CFG_CORE_ASYNC_NOTIF)) 180 notif_register_driver(&console_notif); 181 return TEE_SUCCESS; 182 } 183 driver_init(init_console_itr); 184 #endif 185 186 #ifdef CFG_TZC400 187 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 188 189 static TEE_Result init_tzc400(void) 190 { 191 void *va; 192 193 DMSG("Initializing TZC400"); 194 195 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC, TZC400_REG_SIZE); 196 if (!va) { 197 EMSG("TZC400 not mapped"); 198 panic(); 199 } 200 201 tzc_init((vaddr_t)va); 202 tzc_dump_state(); 203 204 return TEE_SUCCESS; 205 } 206 207 service_init(init_tzc400); 208 #endif /*CFG_TZC400*/ 209 210 #if defined(PLATFORM_FLAVOR_qemu_virt) 211 static void release_secondary_early_hpen(size_t pos) 212 { 213 struct mailbox { 214 uint64_t ep; 215 uint64_t hpen[]; 216 } *mailbox; 217 218 if (cpu_mmu_enabled()) 219 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC, 220 SECRAM_COHERENT_SIZE); 221 else 222 mailbox = (void *)SECRAM_BASE; 223 224 if (!mailbox) 225 panic(); 226 227 mailbox->ep = TEE_LOAD_ADDR; 228 dsb_ishst(); 229 mailbox->hpen[pos] = 1; 230 dsb_ishst(); 231 sev(); 232 } 233 234 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 235 { 236 size_t pos = get_core_pos_mpidr(core_id); 237 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 238 239 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 240 return PSCI_RET_INVALID_PARAMETERS; 241 242 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 243 244 if (core_is_released[pos]) { 245 EMSG("core %zu already released", pos); 246 return PSCI_RET_DENIED; 247 } 248 core_is_released[pos] = true; 249 250 boot_set_core_ns_entry(pos, entry, context_id); 251 release_secondary_early_hpen(pos); 252 253 return PSCI_RET_SUCCESS; 254 } 255 #endif /*PLATFORM_FLAVOR_qemu_virt*/ 256