1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #include <arm.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/pl011.h> 11 #include <drivers/tzc400.h> 12 #include <initcall.h> 13 #include <keep.h> 14 #include <kernel/generic_boot.h> 15 #include <kernel/interrupt.h> 16 #include <kernel/misc.h> 17 #include <kernel/panic.h> 18 #include <kernel/pm_stubs.h> 19 #include <kernel/tee_time.h> 20 #include <mm/core_memprot.h> 21 #include <mm/core_mmu.h> 22 #include <platform_config.h> 23 #include <sm/psci.h> 24 #include <stdint.h> 25 #include <string.h> 26 #include <tee/entry_fast.h> 27 #include <tee/entry_std.h> 28 #include <trace.h> 29 30 static const struct thread_handlers handlers = { 31 #if defined(CFG_WITH_ARM_TRUSTED_FW) 32 .cpu_on = cpu_on_handler, 33 .cpu_off = pm_do_nothing, 34 .cpu_suspend = pm_do_nothing, 35 .cpu_resume = pm_do_nothing, 36 .system_off = pm_do_nothing, 37 .system_reset = pm_do_nothing, 38 #else 39 .cpu_on = pm_panic, 40 .cpu_off = pm_panic, 41 .cpu_suspend = pm_panic, 42 .cpu_resume = pm_panic, 43 .system_off = pm_panic, 44 .system_reset = pm_panic, 45 #endif 46 }; 47 48 static struct gic_data gic_data __nex_bss; 49 static struct pl011_data console_data __nex_bss; 50 51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 52 #if defined(PLATFORM_FLAVOR_fvp) 53 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE); 54 #endif 55 #if defined(PLATFORM_FLAVOR_qemu_virt) 56 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE); 57 #endif 58 #ifdef DRAM0_BASE 59 register_ddr(DRAM0_BASE, DRAM0_SIZE); 60 #endif 61 #ifdef DRAM1_BASE 62 register_ddr(DRAM1_BASE, DRAM1_SIZE); 63 #endif 64 65 const struct thread_handlers *generic_boot_get_handlers(void) 66 { 67 return &handlers; 68 } 69 70 #ifdef GIC_BASE 71 72 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 73 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); 74 75 void main_init_gic(void) 76 { 77 vaddr_t gicc_base; 78 vaddr_t gicd_base; 79 80 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 81 MEM_AREA_IO_SEC); 82 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 83 MEM_AREA_IO_SEC); 84 if (!gicc_base || !gicd_base) 85 panic(); 86 87 #if defined(CFG_WITH_ARM_TRUSTED_FW) 88 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 89 gic_init_base_addr(&gic_data, gicc_base, gicd_base); 90 #else 91 /* Initialize GIC */ 92 gic_init(&gic_data, gicc_base, gicd_base); 93 #endif 94 itr_init(&gic_data.chip); 95 } 96 97 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 98 void main_secondary_init_gic(void) 99 { 100 gic_cpu_init(&gic_data); 101 } 102 #endif 103 104 #endif 105 106 void itr_core_handler(void) 107 { 108 gic_it_handle(&gic_data); 109 } 110 111 void console_init(void) 112 { 113 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 114 CONSOLE_BAUDRATE); 115 register_serial_console(&console_data.chip); 116 } 117 118 #if defined(IT_CONSOLE_UART) && \ 119 !(defined(CFG_WITH_ARM_TRUSTED_FW) && defined(CFG_ARM_GICV3)) 120 /* 121 * This cannot be enabled with TF-A and GICv3 because TF-A then need to 122 * assign the interrupt number of the UART to OP-TEE (S-EL1). Currently 123 * there's no way of TF-A to know which interrupts that OP-TEE will serve. 124 * If TF-A doesn't assign the interrupt we're enabling below to OP-TEE it 125 * will hang in EL3 since the interrupt will just be delivered again and 126 * again. 127 */ 128 static enum itr_return console_itr_cb(struct itr_handler *h __unused) 129 { 130 struct serial_chip *cons = &console_data.chip; 131 132 while (cons->ops->have_rx_data(cons)) { 133 int ch __maybe_unused = cons->ops->getchar(cons); 134 135 DMSG("cpu %zu: got 0x%x", get_core_pos(), ch); 136 } 137 return ITRR_HANDLED; 138 } 139 140 static struct itr_handler console_itr = { 141 .it = IT_CONSOLE_UART, 142 .flags = ITRF_TRIGGER_LEVEL, 143 .handler = console_itr_cb, 144 }; 145 KEEP_PAGER(console_itr); 146 147 static TEE_Result init_console_itr(void) 148 { 149 itr_add(&console_itr); 150 itr_enable(IT_CONSOLE_UART); 151 return TEE_SUCCESS; 152 } 153 driver_init(init_console_itr); 154 #endif 155 156 #ifdef CFG_TZC400 157 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 158 159 static TEE_Result init_tzc400(void) 160 { 161 void *va; 162 163 DMSG("Initializing TZC400"); 164 165 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC); 166 if (!va) { 167 EMSG("TZC400 not mapped"); 168 panic(); 169 } 170 171 tzc_init((vaddr_t)va); 172 tzc_dump_state(); 173 174 return TEE_SUCCESS; 175 } 176 177 service_init(init_tzc400); 178 #endif /*CFG_TZC400*/ 179 180 #if defined(PLATFORM_FLAVOR_qemu_virt) 181 static void release_secondary_early_hpen(size_t pos) 182 { 183 struct mailbox { 184 uint64_t ep; 185 uint64_t hpen[]; 186 } *mailbox; 187 188 if (cpu_mmu_enabled()) 189 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC); 190 else 191 mailbox = (void *)SECRAM_BASE; 192 193 if (!mailbox) 194 panic(); 195 196 mailbox->ep = TEE_LOAD_ADDR; 197 dsb_ishst(); 198 mailbox->hpen[pos] = 1; 199 dsb_ishst(); 200 sev(); 201 } 202 203 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 204 { 205 size_t pos = get_core_pos_mpidr(core_id); 206 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 207 208 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 209 return PSCI_RET_INVALID_PARAMETERS; 210 211 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 212 213 if (core_is_released[pos]) { 214 EMSG("core %zu already released", pos); 215 return PSCI_RET_DENIED; 216 } 217 core_is_released[pos] = true; 218 219 generic_boot_set_core_ns_entry(pos, entry, context_id); 220 release_secondary_early_hpen(pos); 221 222 return PSCI_RET_SUCCESS; 223 } 224 #endif /*PLATFORM_FLAVOR_qemu_virt*/ 225