1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016-2020, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #include <arm.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/pl011.h> 11 #include <drivers/tzc400.h> 12 #include <initcall.h> 13 #include <keep.h> 14 #include <kernel/boot.h> 15 #include <kernel/interrupt.h> 16 #include <kernel/misc.h> 17 #include <kernel/panic.h> 18 #include <kernel/tee_time.h> 19 #include <mm/core_memprot.h> 20 #include <mm/core_mmu.h> 21 #include <platform_config.h> 22 #include <sm/psci.h> 23 #include <stdint.h> 24 #include <string.h> 25 #include <trace.h> 26 27 static struct gic_data gic_data __nex_bss; 28 static struct pl011_data console_data __nex_bss; 29 30 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 31 #if defined(PLATFORM_FLAVOR_fvp) 32 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE); 33 #endif 34 #if defined(PLATFORM_FLAVOR_qemu_virt) 35 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE); 36 #endif 37 #ifdef DRAM0_BASE 38 register_ddr(DRAM0_BASE, DRAM0_SIZE); 39 #endif 40 #ifdef DRAM1_BASE 41 register_ddr(DRAM1_BASE, DRAM1_SIZE); 42 #endif 43 44 #ifdef GIC_BASE 45 46 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); 48 49 void main_init_gic(void) 50 { 51 vaddr_t gicc_base; 52 vaddr_t gicd_base; 53 54 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 55 MEM_AREA_IO_SEC, GIC_CPU_REG_SIZE); 56 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 57 MEM_AREA_IO_SEC, GIC_DIST_REG_SIZE); 58 if (!gicc_base || !gicd_base) 59 panic(); 60 61 #if defined(CFG_WITH_ARM_TRUSTED_FW) 62 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 63 gic_init_base_addr(&gic_data, gicc_base, gicd_base); 64 #else 65 /* Initialize GIC */ 66 gic_init(&gic_data, gicc_base, gicd_base); 67 #endif 68 itr_init(&gic_data.chip); 69 } 70 71 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 72 void main_secondary_init_gic(void) 73 { 74 gic_cpu_init(&gic_data); 75 } 76 #endif 77 78 #endif 79 80 void itr_core_handler(void) 81 { 82 gic_it_handle(&gic_data); 83 } 84 85 void console_init(void) 86 { 87 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 88 CONSOLE_BAUDRATE); 89 register_serial_console(&console_data.chip); 90 } 91 92 #if defined(IT_CONSOLE_UART) && \ 93 !(defined(CFG_WITH_ARM_TRUSTED_FW) && defined(CFG_ARM_GICV3)) 94 /* 95 * This cannot be enabled with TF-A and GICv3 because TF-A then need to 96 * assign the interrupt number of the UART to OP-TEE (S-EL1). Currently 97 * there's no way of TF-A to know which interrupts that OP-TEE will serve. 98 * If TF-A doesn't assign the interrupt we're enabling below to OP-TEE it 99 * will hang in EL3 since the interrupt will just be delivered again and 100 * again. 101 */ 102 static enum itr_return console_itr_cb(struct itr_handler *h __unused) 103 { 104 struct serial_chip *cons = &console_data.chip; 105 106 while (cons->ops->have_rx_data(cons)) { 107 int ch __maybe_unused = cons->ops->getchar(cons); 108 109 DMSG("cpu %zu: got 0x%x", get_core_pos(), ch); 110 } 111 return ITRR_HANDLED; 112 } 113 114 static struct itr_handler console_itr = { 115 .it = IT_CONSOLE_UART, 116 .flags = ITRF_TRIGGER_LEVEL, 117 .handler = console_itr_cb, 118 }; 119 DECLARE_KEEP_PAGER(console_itr); 120 121 static TEE_Result init_console_itr(void) 122 { 123 itr_add(&console_itr); 124 itr_enable(IT_CONSOLE_UART); 125 return TEE_SUCCESS; 126 } 127 driver_init(init_console_itr); 128 #endif 129 130 #ifdef CFG_TZC400 131 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 132 133 static TEE_Result init_tzc400(void) 134 { 135 void *va; 136 137 DMSG("Initializing TZC400"); 138 139 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC, TZC400_REG_SIZE); 140 if (!va) { 141 EMSG("TZC400 not mapped"); 142 panic(); 143 } 144 145 tzc_init((vaddr_t)va); 146 tzc_dump_state(); 147 148 return TEE_SUCCESS; 149 } 150 151 service_init(init_tzc400); 152 #endif /*CFG_TZC400*/ 153 154 #if defined(PLATFORM_FLAVOR_qemu_virt) 155 static void release_secondary_early_hpen(size_t pos) 156 { 157 struct mailbox { 158 uint64_t ep; 159 uint64_t hpen[]; 160 } *mailbox; 161 162 if (cpu_mmu_enabled()) 163 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC, 164 SECRAM_COHERENT_SIZE); 165 else 166 mailbox = (void *)SECRAM_BASE; 167 168 if (!mailbox) 169 panic(); 170 171 mailbox->ep = TEE_LOAD_ADDR; 172 dsb_ishst(); 173 mailbox->hpen[pos] = 1; 174 dsb_ishst(); 175 sev(); 176 } 177 178 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 179 { 180 size_t pos = get_core_pos_mpidr(core_id); 181 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 182 183 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 184 return PSCI_RET_INVALID_PARAMETERS; 185 186 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 187 188 if (core_is_released[pos]) { 189 EMSG("core %zu already released", pos); 190 return PSCI_RET_DENIED; 191 } 192 core_is_released[pos] = true; 193 194 boot_set_core_ns_entry(pos, entry, context_id); 195 release_secondary_early_hpen(pos); 196 197 return PSCI_RET_SUCCESS; 198 } 199 #endif /*PLATFORM_FLAVOR_qemu_virt*/ 200