1 /* 2 * Copyright (c) 2014, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <platform_config.h> 29 30 #include <stdint.h> 31 #include <string.h> 32 33 #include <drivers/gic.h> 34 #include <drivers/pl011.h> 35 36 #include <arm.h> 37 #include <kernel/generic_boot.h> 38 #include <kernel/pm_stubs.h> 39 #include <trace.h> 40 #include <kernel/misc.h> 41 #include <kernel/tee_time.h> 42 #include <tee/entry_fast.h> 43 #include <tee/entry_std.h> 44 #include <console.h> 45 46 static void main_fiq(void); 47 48 static const struct thread_handlers handlers = { 49 .std_smc = tee_entry_std, 50 .fast_smc = tee_entry_fast, 51 .fiq = main_fiq, 52 #if defined(CFG_WITH_ARM_TRUSTED_FW) 53 .cpu_on = cpu_on_handler, 54 .cpu_off = pm_do_nothing, 55 .cpu_suspend = pm_do_nothing, 56 .cpu_resume = pm_do_nothing, 57 .system_off = pm_do_nothing, 58 .system_reset = pm_do_nothing, 59 #else 60 .cpu_on = pm_panic, 61 .cpu_off = pm_panic, 62 .cpu_suspend = pm_panic, 63 .cpu_resume = pm_panic, 64 .system_off = pm_panic, 65 .system_reset = pm_panic, 66 #endif 67 }; 68 69 const struct thread_handlers *generic_boot_get_handlers(void) 70 { 71 return &handlers; 72 } 73 74 #if PLATFORM_FLAVOR_IS(fvp) || PLATFORM_FLAVOR_IS(juno) 75 void main_init_gic(void) 76 { 77 /* 78 * On ARMv8, GIC configuration is initialized in ARM-TF, 79 */ 80 gic_init_base_addr(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 81 gic_it_add(IT_CONSOLE_UART); 82 /* Route FIQ to primary CPU */ 83 gic_it_set_cpu_mask(IT_CONSOLE_UART, gic_it_get_target(0)); 84 gic_it_set_prio(IT_CONSOLE_UART, 0x1); 85 gic_it_enable(IT_CONSOLE_UART); 86 87 } 88 #elif PLATFORM_FLAVOR_IS(qemu_virt) 89 void main_init_gic(void) 90 { 91 /* Initialize GIC */ 92 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 93 gic_it_add(IT_CONSOLE_UART); 94 gic_it_set_cpu_mask(IT_CONSOLE_UART, 0x1); 95 gic_it_set_prio(IT_CONSOLE_UART, 0x1); 96 gic_it_enable(IT_CONSOLE_UART); 97 } 98 #endif 99 100 static void main_fiq(void) 101 { 102 uint32_t iar; 103 104 DMSG("enter"); 105 106 iar = gic_read_iar(); 107 108 while (pl011_have_rx_data(CONSOLE_UART_BASE)) { 109 int ch __maybe_unused = pl011_getchar(CONSOLE_UART_BASE); 110 111 DMSG("cpu %zu: got 0x%x", get_core_pos(), ch); 112 } 113 114 gic_write_eoir(iar); 115 116 DMSG("return"); 117 } 118 119 void console_init(void) 120 { 121 pl011_init(CONSOLE_UART_BASE, 122 CONSOLE_UART_CLK_IN_HZ, 123 CONSOLE_BAUDRATE); 124 } 125 126 void console_putc(int ch) 127 { 128 pl011_putc(ch, CONSOLE_UART_BASE); 129 if (ch == '\n') 130 pl011_putc('\r', CONSOLE_UART_BASE); 131 } 132 133 void console_flush(void) 134 { 135 pl011_flush(CONSOLE_UART_BASE); 136 } 137