1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016-2020, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #include <arm.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/hfic.h> 11 #include <drivers/pl011.h> 12 #include <drivers/tzc400.h> 13 #include <initcall.h> 14 #include <keep.h> 15 #include <kernel/boot.h> 16 #include <kernel/interrupt.h> 17 #include <kernel/misc.h> 18 #include <kernel/notif.h> 19 #include <kernel/panic.h> 20 #include <kernel/spinlock.h> 21 #include <kernel/tee_time.h> 22 #include <mm/core_memprot.h> 23 #include <mm/core_mmu.h> 24 #include <platform_config.h> 25 #include <sm/psci.h> 26 #include <stdint.h> 27 #include <string.h> 28 #include <trace.h> 29 30 static struct pl011_data console_data __nex_bss; 31 32 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 33 #if defined(PLATFORM_FLAVOR_fvp) 34 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE); 35 #endif 36 #if defined(PLATFORM_FLAVOR_qemu_virt) 37 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE); 38 #endif 39 #ifdef DRAM0_BASE 40 register_ddr(DRAM0_BASE, DRAM0_SIZE); 41 #endif 42 #ifdef DRAM1_BASE 43 register_ddr(DRAM1_BASE, DRAM1_SIZE); 44 #endif 45 46 #ifdef CFG_GIC 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 49 #ifdef GIC_REDIST_BASE 50 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_REDIST_BASE, GIC_REDIST_SIZE); 51 #endif 52 53 void boot_primary_init_intc(void) 54 { 55 #ifdef GIC_REDIST_BASE 56 gic_init_v3(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET, 57 GIC_REDIST_BASE); 58 #else 59 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 60 #endif 61 } 62 63 void boot_secondary_init_intc(void) 64 { 65 gic_init_per_cpu(); 66 } 67 #endif /*CFG_GIC*/ 68 69 #ifdef CFG_CORE_HAFNIUM_INTC 70 void boot_primary_init_intc(void) 71 { 72 hfic_init(); 73 } 74 #endif 75 76 void console_init(void) 77 { 78 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 79 CONSOLE_BAUDRATE); 80 register_serial_console(&console_data.chip); 81 } 82 83 #if (defined(CFG_GIC) || defined(CFG_CORE_HAFNIUM_INTC)) && \ 84 defined(IT_CONSOLE_UART) && \ 85 !defined(CFG_NS_VIRTUALIZATION) && \ 86 !(defined(CFG_WITH_ARM_TRUSTED_FW) && defined(CFG_ARM_GICV2)) 87 /* 88 * This cannot be enabled with TF-A and GICv3 because TF-A then need to 89 * assign the interrupt number of the UART to OP-TEE (S-EL1). Currently 90 * there's no way of TF-A to know which interrupts that OP-TEE will serve. 91 * If TF-A doesn't assign the interrupt we're enabling below to OP-TEE it 92 * will hang in EL3 since the interrupt will just be delivered again and 93 * again. 94 */ 95 96 static void read_console(void) 97 { 98 struct serial_chip *cons = &console_data.chip; 99 100 if (!cons->ops->getchar || !cons->ops->have_rx_data) 101 return; 102 103 while (cons->ops->have_rx_data(cons)) { 104 int ch __maybe_unused = cons->ops->getchar(cons); 105 106 DMSG("got 0x%x", ch); 107 } 108 } 109 110 static enum itr_return console_itr_cb(struct itr_handler *hdl) 111 { 112 if (notif_async_is_started()) { 113 /* 114 * Asynchronous notifications are enabled, lets read from 115 * uart in the bottom half instead. 116 */ 117 interrupt_disable(hdl->chip, hdl->it); 118 notif_send_async(NOTIF_VALUE_DO_BOTTOM_HALF); 119 } else { 120 read_console(); 121 } 122 return ITRR_HANDLED; 123 } 124 125 static struct itr_handler console_itr = { 126 .it = IT_CONSOLE_UART, 127 .flags = ITRF_TRIGGER_LEVEL, 128 .handler = console_itr_cb, 129 }; 130 DECLARE_KEEP_PAGER(console_itr); 131 132 static void atomic_console_notif(struct notif_driver *ndrv __unused, 133 enum notif_event ev __maybe_unused) 134 { 135 DMSG("Asynchronous notifications started, event %d", (int)ev); 136 } 137 DECLARE_KEEP_PAGER(atomic_console_notif); 138 139 static void yielding_console_notif(struct notif_driver *ndrv __unused, 140 enum notif_event ev) 141 { 142 switch (ev) { 143 case NOTIF_EVENT_DO_BOTTOM_HALF: 144 read_console(); 145 interrupt_enable(console_itr.chip, console_itr.it); 146 break; 147 case NOTIF_EVENT_STOPPED: 148 DMSG("Asynchronous notifications stopped"); 149 interrupt_enable(console_itr.chip, console_itr.it); 150 break; 151 default: 152 EMSG("Unknown event %d", (int)ev); 153 } 154 } 155 156 struct notif_driver console_notif = { 157 .atomic_cb = atomic_console_notif, 158 .yielding_cb = yielding_console_notif, 159 }; 160 161 static TEE_Result init_console_itr(void) 162 { 163 TEE_Result res = TEE_ERROR_GENERIC; 164 165 res = interrupt_add_handler_with_chip(interrupt_get_main_chip(), 166 &console_itr); 167 if (res) 168 return res; 169 170 interrupt_enable(console_itr.chip, console_itr.it); 171 172 if (IS_ENABLED(CFG_CORE_ASYNC_NOTIF)) 173 notif_register_driver(&console_notif); 174 return TEE_SUCCESS; 175 } 176 driver_init(init_console_itr); 177 #endif 178 179 #ifdef CFG_TZC400 180 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 181 182 static TEE_Result init_tzc400(void) 183 { 184 void *va; 185 186 DMSG("Initializing TZC400"); 187 188 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC, TZC400_REG_SIZE); 189 if (!va) { 190 EMSG("TZC400 not mapped"); 191 panic(); 192 } 193 194 tzc_init((vaddr_t)va); 195 tzc_dump_state(); 196 197 return TEE_SUCCESS; 198 } 199 200 service_init(init_tzc400); 201 #endif /*CFG_TZC400*/ 202 203 #if defined(PLATFORM_FLAVOR_qemu_virt) 204 static void release_secondary_early_hpen(size_t pos) 205 { 206 struct mailbox { 207 uint64_t ep; 208 uint64_t hpen[]; 209 } *mailbox; 210 211 if (cpu_mmu_enabled()) 212 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC, 213 SECRAM_COHERENT_SIZE); 214 else 215 mailbox = (void *)SECRAM_BASE; 216 217 if (!mailbox) 218 panic(); 219 220 mailbox->ep = TEE_LOAD_ADDR; 221 dsb_ishst(); 222 mailbox->hpen[pos] = 1; 223 dsb_ishst(); 224 sev(); 225 } 226 227 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 228 { 229 size_t pos = get_core_pos_mpidr(core_id); 230 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 231 232 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 233 return PSCI_RET_INVALID_PARAMETERS; 234 235 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 236 237 if (core_is_released[pos]) { 238 EMSG("core %zu already released", pos); 239 return PSCI_RET_DENIED; 240 } 241 core_is_released[pos] = true; 242 243 boot_set_core_ns_entry(pos, entry, context_id); 244 release_secondary_early_hpen(pos); 245 246 return PSCI_RET_SUCCESS; 247 } 248 #endif /*PLATFORM_FLAVOR_qemu_virt*/ 249