1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016-2023, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #include <arm.h> 8 #include <config.h> 9 #include <console.h> 10 #include <drivers/gic.h> 11 #include <drivers/hfic.h> 12 #include <drivers/pl011.h> 13 #include <drivers/tzc400.h> 14 #include <initcall.h> 15 #include <keep.h> 16 #include <kernel/boot.h> 17 #include <kernel/interrupt.h> 18 #include <kernel/misc.h> 19 #include <kernel/notif.h> 20 #include <kernel/panic.h> 21 #include <kernel/thread_spmc.h> 22 #include <mm/core_memprot.h> 23 #include <mm/core_mmu.h> 24 #include <platform_config.h> 25 #include <sm/psci.h> 26 #include <stdint.h> 27 #include <trace.h> 28 29 static struct pl011_data console_data __nex_bss; 30 31 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 32 #if defined(PLATFORM_FLAVOR_fvp) 33 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE); 34 #endif 35 #if defined(PLATFORM_FLAVOR_qemu_virt) 36 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE); 37 #endif 38 #ifdef DRAM0_BASE 39 register_ddr(DRAM0_BASE, DRAM0_SIZE); 40 #endif 41 #ifdef DRAM1_BASE 42 register_ddr(DRAM1_BASE, DRAM1_SIZE); 43 #endif 44 45 #ifdef CFG_GIC 46 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE); 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 48 #ifdef GIC_REDIST_BASE 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_REDIST_BASE, GIC_REDIST_SIZE); 50 #endif 51 52 void boot_primary_init_intc(void) 53 { 54 #ifdef GIC_REDIST_BASE 55 gic_init_v3(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET, 56 GIC_REDIST_BASE); 57 #else 58 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 59 #endif 60 if (IS_ENABLED(CFG_CORE_SEL1_SPMC) && 61 IS_ENABLED(CFG_CORE_ASYNC_NOTIF)) { 62 size_t it = CFG_CORE_ASYNC_NOTIF_GIC_INTID; 63 64 if (it >= GIC_SGI_SEC_BASE && it <= GIC_SGI_SEC_MAX) 65 gic_init_donate_sgi_to_ns(it); 66 thread_spmc_set_async_notif_intid(it); 67 } 68 } 69 70 void boot_secondary_init_intc(void) 71 { 72 gic_init_per_cpu(); 73 } 74 #endif /*CFG_GIC*/ 75 76 #ifdef CFG_CORE_HAFNIUM_INTC 77 void boot_primary_init_intc(void) 78 { 79 hfic_init(); 80 } 81 #endif 82 83 void console_init(void) 84 { 85 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 86 CONSOLE_BAUDRATE); 87 register_serial_console(&console_data.chip); 88 } 89 90 #if (defined(CFG_GIC) || defined(CFG_CORE_HAFNIUM_INTC)) && \ 91 defined(IT_CONSOLE_UART) && \ 92 !defined(CFG_NS_VIRTUALIZATION) && \ 93 !(defined(CFG_WITH_ARM_TRUSTED_FW) && defined(CFG_ARM_GICV2)) 94 /* 95 * This cannot be enabled with TF-A and GICv3 because TF-A then need to 96 * assign the interrupt number of the UART to OP-TEE (S-EL1). Currently 97 * there's no way of TF-A to know which interrupts that OP-TEE will serve. 98 * If TF-A doesn't assign the interrupt we're enabling below to OP-TEE it 99 * will hang in EL3 since the interrupt will just be delivered again and 100 * again. 101 */ 102 103 static void read_console(void) 104 { 105 struct serial_chip *cons = &console_data.chip; 106 107 if (!cons->ops->getchar || !cons->ops->have_rx_data) 108 return; 109 110 while (cons->ops->have_rx_data(cons)) { 111 int ch __maybe_unused = cons->ops->getchar(cons); 112 113 DMSG("got 0x%x", ch); 114 } 115 } 116 117 static enum itr_return console_itr_cb(struct itr_handler *hdl __unused) 118 { 119 if (notif_async_is_started()) { 120 /* 121 * Asynchronous notifications are enabled, lets read from 122 * uart in the bottom half instead. 123 */ 124 console_data.chip.ops->rx_intr_disable(&console_data.chip); 125 notif_send_async(NOTIF_VALUE_DO_BOTTOM_HALF); 126 } else { 127 read_console(); 128 } 129 return ITRR_HANDLED; 130 } 131 132 static struct itr_handler console_itr = { 133 .it = IT_CONSOLE_UART, 134 .flags = ITRF_TRIGGER_LEVEL, 135 .handler = console_itr_cb, 136 }; 137 DECLARE_KEEP_PAGER(console_itr); 138 139 static void atomic_console_notif(struct notif_driver *ndrv __unused, 140 enum notif_event ev __maybe_unused) 141 { 142 DMSG("Asynchronous notifications started, event %d", (int)ev); 143 } 144 DECLARE_KEEP_PAGER(atomic_console_notif); 145 146 static void yielding_console_notif(struct notif_driver *ndrv __unused, 147 enum notif_event ev) 148 { 149 switch (ev) { 150 case NOTIF_EVENT_DO_BOTTOM_HALF: 151 read_console(); 152 console_data.chip.ops->rx_intr_enable(&console_data.chip); 153 break; 154 case NOTIF_EVENT_STOPPED: 155 DMSG("Asynchronous notifications stopped"); 156 console_data.chip.ops->rx_intr_enable(&console_data.chip); 157 break; 158 default: 159 EMSG("Unknown event %d", (int)ev); 160 } 161 } 162 163 struct notif_driver console_notif = { 164 .atomic_cb = atomic_console_notif, 165 .yielding_cb = yielding_console_notif, 166 }; 167 168 static TEE_Result init_console_itr(void) 169 { 170 TEE_Result res = TEE_ERROR_GENERIC; 171 bool have_itr_ctrl = console_data.chip.ops->rx_intr_enable && 172 console_data.chip.ops->rx_intr_disable; 173 174 res = interrupt_add_handler_with_chip(interrupt_get_main_chip(), 175 &console_itr); 176 if (res) 177 return res; 178 179 interrupt_enable(console_itr.chip, console_itr.it); 180 181 if (IS_ENABLED(CFG_CORE_ASYNC_NOTIF) && have_itr_ctrl) 182 notif_register_driver(&console_notif); 183 return TEE_SUCCESS; 184 } 185 driver_init(init_console_itr); 186 #endif 187 188 #ifdef CFG_TZC400 189 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 190 191 static TEE_Result init_tzc400(void) 192 { 193 void *va; 194 195 DMSG("Initializing TZC400"); 196 197 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC, TZC400_REG_SIZE); 198 if (!va) { 199 EMSG("TZC400 not mapped"); 200 panic(); 201 } 202 203 tzc_init((vaddr_t)va); 204 tzc_dump_state(); 205 206 return TEE_SUCCESS; 207 } 208 209 service_init(init_tzc400); 210 #endif /*CFG_TZC400*/ 211 212 #if defined(PLATFORM_FLAVOR_qemu_virt) 213 static void release_secondary_early_hpen(size_t pos) 214 { 215 struct mailbox { 216 uint64_t ep; 217 uint64_t hpen[]; 218 } *mailbox; 219 220 if (cpu_mmu_enabled()) 221 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC, 222 SECRAM_COHERENT_SIZE); 223 else 224 mailbox = (void *)SECRAM_BASE; 225 226 if (!mailbox) 227 panic(); 228 229 mailbox->ep = TEE_LOAD_ADDR; 230 dsb_ishst(); 231 mailbox->hpen[pos] = 1; 232 dsb_ishst(); 233 sev(); 234 } 235 236 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 237 { 238 size_t pos = get_core_pos_mpidr(core_id); 239 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 240 241 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 242 return PSCI_RET_INVALID_PARAMETERS; 243 244 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 245 246 if (core_is_released[pos]) { 247 EMSG("core %zu already released", pos); 248 return PSCI_RET_DENIED; 249 } 250 core_is_released[pos] = true; 251 252 boot_set_core_ns_entry(pos, entry, context_id); 253 release_secondary_early_hpen(pos); 254 255 return PSCI_RET_SUCCESS; 256 } 257 #endif /*PLATFORM_FLAVOR_qemu_virt*/ 258