1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016-2020, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #include <arm.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/hfic.h> 11 #include <drivers/pl011.h> 12 #include <drivers/tpm2_mmio.h> 13 #include <drivers/tpm2_ptp_fifo.h> 14 #include <drivers/tzc400.h> 15 #include <initcall.h> 16 #include <keep.h> 17 #include <kernel/boot.h> 18 #include <kernel/interrupt.h> 19 #include <kernel/misc.h> 20 #include <kernel/notif.h> 21 #include <kernel/panic.h> 22 #include <kernel/spinlock.h> 23 #include <kernel/tee_time.h> 24 #include <mm/core_memprot.h> 25 #include <mm/core_mmu.h> 26 #include <platform_config.h> 27 #include <sm/psci.h> 28 #include <stdint.h> 29 #include <string.h> 30 #include <trace.h> 31 32 static struct gic_data gic_data __maybe_unused __nex_bss; 33 static struct hfic_data hfic_data __maybe_unused __nex_bss; 34 static struct pl011_data console_data __nex_bss; 35 36 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 37 #if defined(CFG_DRIVERS_TPM2_MMIO) 38 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TPM2_BASE, TPM2_REG_SIZE); 39 #endif 40 #if defined(PLATFORM_FLAVOR_fvp) 41 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE); 42 #endif 43 #if defined(PLATFORM_FLAVOR_qemu_virt) 44 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE); 45 #endif 46 #ifdef DRAM0_BASE 47 register_ddr(DRAM0_BASE, DRAM0_SIZE); 48 #endif 49 #ifdef DRAM1_BASE 50 register_ddr(DRAM1_BASE, DRAM1_SIZE); 51 #endif 52 53 #ifdef CFG_GIC 54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 55 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); 56 57 void main_init_gic(void) 58 { 59 #if defined(CFG_WITH_ARM_TRUSTED_FW) 60 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 61 gic_init_base_addr(&gic_data, GIC_BASE + GICC_OFFSET, 62 GIC_BASE + GICD_OFFSET); 63 #else 64 gic_init(&gic_data, GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 65 #endif 66 itr_init(&gic_data.chip); 67 } 68 69 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 70 void main_secondary_init_gic(void) 71 { 72 gic_cpu_init(&gic_data); 73 } 74 #endif 75 76 void itr_core_handler(void) 77 { 78 gic_it_handle(&gic_data); 79 } 80 #endif /*CFG_GIC*/ 81 82 #ifdef CFG_CORE_HAFNIUM_INTC 83 void main_init_gic(void) 84 { 85 hfic_init(&hfic_data); 86 itr_init(&hfic_data.chip); 87 } 88 89 void itr_core_handler(void) 90 { 91 hfic_it_handle(&hfic_data); 92 } 93 #endif 94 95 void console_init(void) 96 { 97 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 98 CONSOLE_BAUDRATE); 99 register_serial_console(&console_data.chip); 100 } 101 102 #if (defined(CFG_GIC) || defined(CFG_CORE_HAFNIUM_INTC)) && \ 103 defined(IT_CONSOLE_UART) && \ 104 !defined(CFG_NS_VIRTUALIZATION) && \ 105 !(defined(CFG_WITH_ARM_TRUSTED_FW) && defined(CFG_ARM_GICV2)) 106 /* 107 * This cannot be enabled with TF-A and GICv3 because TF-A then need to 108 * assign the interrupt number of the UART to OP-TEE (S-EL1). Currently 109 * there's no way of TF-A to know which interrupts that OP-TEE will serve. 110 * If TF-A doesn't assign the interrupt we're enabling below to OP-TEE it 111 * will hang in EL3 since the interrupt will just be delivered again and 112 * again. 113 */ 114 115 static void read_console(void) 116 { 117 struct serial_chip *cons = &console_data.chip; 118 119 if (!cons->ops->getchar || !cons->ops->have_rx_data) 120 return; 121 122 while (cons->ops->have_rx_data(cons)) { 123 int ch __maybe_unused = cons->ops->getchar(cons); 124 125 DMSG("got 0x%x", ch); 126 } 127 } 128 129 static enum itr_return console_itr_cb(struct itr_handler *h __maybe_unused) 130 { 131 if (notif_async_is_started()) { 132 /* 133 * Asynchronous notifications are enabled, lets read from 134 * uart in the bottom half instead. 135 */ 136 itr_disable(IT_CONSOLE_UART); 137 notif_send_async(NOTIF_VALUE_DO_BOTTOM_HALF); 138 } else { 139 read_console(); 140 } 141 return ITRR_HANDLED; 142 } 143 144 static struct itr_handler console_itr = { 145 .it = IT_CONSOLE_UART, 146 .flags = ITRF_TRIGGER_LEVEL, 147 .handler = console_itr_cb, 148 }; 149 DECLARE_KEEP_PAGER(console_itr); 150 151 static void atomic_console_notif(struct notif_driver *ndrv __unused, 152 enum notif_event ev __maybe_unused) 153 { 154 DMSG("Asynchronous notifications started, event %d", (int)ev); 155 } 156 DECLARE_KEEP_PAGER(atomic_console_notif); 157 158 static void yielding_console_notif(struct notif_driver *ndrv __unused, 159 enum notif_event ev) 160 { 161 switch (ev) { 162 case NOTIF_EVENT_DO_BOTTOM_HALF: 163 read_console(); 164 itr_enable(IT_CONSOLE_UART); 165 break; 166 case NOTIF_EVENT_STOPPED: 167 DMSG("Asynchronous notifications stopped"); 168 itr_enable(IT_CONSOLE_UART); 169 break; 170 default: 171 EMSG("Unknown event %d", (int)ev); 172 } 173 } 174 175 struct notif_driver console_notif = { 176 .atomic_cb = atomic_console_notif, 177 .yielding_cb = yielding_console_notif, 178 }; 179 180 static TEE_Result init_console_itr(void) 181 { 182 itr_add(&console_itr); 183 itr_enable(IT_CONSOLE_UART); 184 if (IS_ENABLED(CFG_CORE_ASYNC_NOTIF)) 185 notif_register_driver(&console_notif); 186 return TEE_SUCCESS; 187 } 188 driver_init(init_console_itr); 189 #endif 190 191 #if defined(CFG_DRIVERS_TPM2_MMIO) 192 static TEE_Result init_tpm2(void) 193 { 194 enum tpm2_result res = TPM2_OK; 195 196 res = tpm2_mmio_init(TPM2_BASE); 197 if (res) { 198 EMSG("Failed to initialize TPM2 MMIO"); 199 return TEE_ERROR_GENERIC; 200 } 201 202 DMSG("TPM2 Chip initialized"); 203 204 return TEE_SUCCESS; 205 } 206 driver_init(init_tpm2); 207 #endif /* defined(CFG_DRIVERS_TPM2_MMIO) */ 208 209 #ifdef CFG_TZC400 210 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 211 212 static TEE_Result init_tzc400(void) 213 { 214 void *va; 215 216 DMSG("Initializing TZC400"); 217 218 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC, TZC400_REG_SIZE); 219 if (!va) { 220 EMSG("TZC400 not mapped"); 221 panic(); 222 } 223 224 tzc_init((vaddr_t)va); 225 tzc_dump_state(); 226 227 return TEE_SUCCESS; 228 } 229 230 service_init(init_tzc400); 231 #endif /*CFG_TZC400*/ 232 233 #if defined(PLATFORM_FLAVOR_qemu_virt) 234 static void release_secondary_early_hpen(size_t pos) 235 { 236 struct mailbox { 237 uint64_t ep; 238 uint64_t hpen[]; 239 } *mailbox; 240 241 if (cpu_mmu_enabled()) 242 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC, 243 SECRAM_COHERENT_SIZE); 244 else 245 mailbox = (void *)SECRAM_BASE; 246 247 if (!mailbox) 248 panic(); 249 250 mailbox->ep = TEE_LOAD_ADDR; 251 dsb_ishst(); 252 mailbox->hpen[pos] = 1; 253 dsb_ishst(); 254 sev(); 255 } 256 257 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 258 { 259 size_t pos = get_core_pos_mpidr(core_id); 260 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 261 262 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 263 return PSCI_RET_INVALID_PARAMETERS; 264 265 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 266 267 if (core_is_released[pos]) { 268 EMSG("core %zu already released", pos); 269 return PSCI_RET_DENIED; 270 } 271 core_is_released[pos] = true; 272 273 boot_set_core_ns_entry(pos, entry, context_id); 274 release_secondary_early_hpen(pos); 275 276 return PSCI_RET_SUCCESS; 277 } 278 #endif /*PLATFORM_FLAVOR_qemu_virt*/ 279