1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016-2020, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #include <arm.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/pl011.h> 11 #include <drivers/tpm2_mmio.h> 12 #include <drivers/tpm2_ptp_fifo.h> 13 #include <drivers/tzc400.h> 14 #include <initcall.h> 15 #include <keep.h> 16 #include <kernel/boot.h> 17 #include <kernel/interrupt.h> 18 #include <kernel/misc.h> 19 #include <kernel/notif.h> 20 #include <kernel/panic.h> 21 #include <kernel/spinlock.h> 22 #include <kernel/tee_time.h> 23 #include <mm/core_memprot.h> 24 #include <mm/core_mmu.h> 25 #include <platform_config.h> 26 #include <sm/psci.h> 27 #include <stdint.h> 28 #include <string.h> 29 #include <trace.h> 30 31 static struct gic_data gic_data __nex_bss; 32 static struct pl011_data console_data __nex_bss; 33 34 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 35 #if defined(CFG_DRIVERS_TPM2_MMIO) 36 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TPM2_BASE, TPM2_REG_SIZE); 37 #endif 38 #if defined(PLATFORM_FLAVOR_fvp) 39 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE); 40 #endif 41 #if defined(PLATFORM_FLAVOR_qemu_virt) 42 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE); 43 #endif 44 #ifdef DRAM0_BASE 45 register_ddr(DRAM0_BASE, DRAM0_SIZE); 46 #endif 47 #ifdef DRAM1_BASE 48 register_ddr(DRAM1_BASE, DRAM1_SIZE); 49 #endif 50 51 #ifdef GIC_BASE 52 53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); 55 56 void main_init_gic(void) 57 { 58 #if defined(CFG_WITH_ARM_TRUSTED_FW) 59 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 60 gic_init_base_addr(&gic_data, GIC_BASE + GICC_OFFSET, 61 GIC_BASE + GICD_OFFSET); 62 #else 63 gic_init(&gic_data, GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 64 #endif 65 itr_init(&gic_data.chip); 66 } 67 68 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 69 void main_secondary_init_gic(void) 70 { 71 gic_cpu_init(&gic_data); 72 } 73 #endif 74 75 #endif 76 77 void itr_core_handler(void) 78 { 79 gic_it_handle(&gic_data); 80 } 81 82 void console_init(void) 83 { 84 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 85 CONSOLE_BAUDRATE); 86 register_serial_console(&console_data.chip); 87 } 88 89 #if defined(IT_CONSOLE_UART) && !defined(CFG_VIRTUALIZATION) && \ 90 !(defined(CFG_WITH_ARM_TRUSTED_FW) && defined(CFG_ARM_GICV2)) 91 /* 92 * This cannot be enabled with TF-A and GICv3 because TF-A then need to 93 * assign the interrupt number of the UART to OP-TEE (S-EL1). Currently 94 * there's no way of TF-A to know which interrupts that OP-TEE will serve. 95 * If TF-A doesn't assign the interrupt we're enabling below to OP-TEE it 96 * will hang in EL3 since the interrupt will just be delivered again and 97 * again. 98 */ 99 100 static void read_console(void) 101 { 102 struct serial_chip *cons = &console_data.chip; 103 104 while (cons->ops->have_rx_data(cons)) { 105 int ch __maybe_unused = cons->ops->getchar(cons); 106 107 DMSG("got 0x%x", ch); 108 } 109 } 110 111 static enum itr_return console_itr_cb(struct itr_handler *h __maybe_unused) 112 { 113 if (notif_async_is_started()) { 114 /* 115 * Asynchronous notifications are enabled, lets read from 116 * uart in the bottom half instead. 117 */ 118 itr_disable(IT_CONSOLE_UART); 119 notif_send_async(NOTIF_VALUE_DO_BOTTOM_HALF); 120 } else { 121 read_console(); 122 } 123 return ITRR_HANDLED; 124 } 125 126 static struct itr_handler console_itr = { 127 .it = IT_CONSOLE_UART, 128 .flags = ITRF_TRIGGER_LEVEL, 129 .handler = console_itr_cb, 130 }; 131 DECLARE_KEEP_PAGER(console_itr); 132 133 static void atomic_console_notif(struct notif_driver *ndrv __unused, 134 enum notif_event ev __maybe_unused) 135 { 136 DMSG("Asynchronous notifications started, event %d", (int)ev); 137 } 138 DECLARE_KEEP_PAGER(atomic_console_notif); 139 140 static void yielding_console_notif(struct notif_driver *ndrv __unused, 141 enum notif_event ev) 142 { 143 switch (ev) { 144 case NOTIF_EVENT_DO_BOTTOM_HALF: 145 read_console(); 146 itr_enable(IT_CONSOLE_UART); 147 break; 148 case NOTIF_EVENT_STOPPED: 149 DMSG("Asynchronous notifications stopped"); 150 itr_enable(IT_CONSOLE_UART); 151 break; 152 default: 153 EMSG("Unknown event %d", (int)ev); 154 } 155 } 156 157 struct notif_driver console_notif = { 158 .atomic_cb = atomic_console_notif, 159 .yielding_cb = yielding_console_notif, 160 }; 161 162 static TEE_Result init_console_itr(void) 163 { 164 itr_add(&console_itr); 165 itr_enable(IT_CONSOLE_UART); 166 if (IS_ENABLED(CFG_CORE_ASYNC_NOTIF)) 167 notif_register_driver(&console_notif); 168 return TEE_SUCCESS; 169 } 170 driver_init(init_console_itr); 171 #endif 172 173 #if defined(CFG_DRIVERS_TPM2_MMIO) 174 static TEE_Result init_tpm2(void) 175 { 176 enum tpm2_result res = TPM2_OK; 177 178 res = tpm2_mmio_init(TPM2_BASE); 179 if (res) { 180 EMSG("Failed to initialize TPM2 MMIO"); 181 return TEE_ERROR_GENERIC; 182 } 183 184 DMSG("TPM2 Chip initialized"); 185 186 return TEE_SUCCESS; 187 } 188 driver_init(init_tpm2); 189 #endif /* defined(CFG_DRIVERS_TPM2_MMIO) */ 190 191 #ifdef CFG_TZC400 192 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 193 194 static TEE_Result init_tzc400(void) 195 { 196 void *va; 197 198 DMSG("Initializing TZC400"); 199 200 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC, TZC400_REG_SIZE); 201 if (!va) { 202 EMSG("TZC400 not mapped"); 203 panic(); 204 } 205 206 tzc_init((vaddr_t)va); 207 tzc_dump_state(); 208 209 return TEE_SUCCESS; 210 } 211 212 service_init(init_tzc400); 213 #endif /*CFG_TZC400*/ 214 215 #if defined(PLATFORM_FLAVOR_qemu_virt) 216 static void release_secondary_early_hpen(size_t pos) 217 { 218 struct mailbox { 219 uint64_t ep; 220 uint64_t hpen[]; 221 } *mailbox; 222 223 if (cpu_mmu_enabled()) 224 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC, 225 SECRAM_COHERENT_SIZE); 226 else 227 mailbox = (void *)SECRAM_BASE; 228 229 if (!mailbox) 230 panic(); 231 232 mailbox->ep = TEE_LOAD_ADDR; 233 dsb_ishst(); 234 mailbox->hpen[pos] = 1; 235 dsb_ishst(); 236 sev(); 237 } 238 239 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 240 { 241 size_t pos = get_core_pos_mpidr(core_id); 242 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 243 244 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 245 return PSCI_RET_INVALID_PARAMETERS; 246 247 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 248 249 if (core_is_released[pos]) { 250 EMSG("core %zu already released", pos); 251 return PSCI_RET_DENIED; 252 } 253 core_is_released[pos] = true; 254 255 boot_set_core_ns_entry(pos, entry, context_id); 256 release_secondary_early_hpen(pos); 257 258 return PSCI_RET_SUCCESS; 259 } 260 #endif /*PLATFORM_FLAVOR_qemu_virt*/ 261