159a0f5d0SAkshay Belsare# SPDX-License-Identifier: BSD-2-Clause 259a0f5d0SAkshay Belsare# 359a0f5d0SAkshay Belsare# Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved. 459a0f5d0SAkshay Belsare# 559a0f5d0SAkshay Belsare# 659a0f5d0SAkshay Belsare 759a0f5d0SAkshay BelsarePLATFORM_FLAVOR ?= generic 859a0f5d0SAkshay Belsare 959a0f5d0SAkshay Belsareinclude core/arch/arm/cpu/cortex-armv8-0.mk 1059a0f5d0SAkshay Belsare 1159a0f5d0SAkshay BelsareCFG_MMAP_REGIONS ?= 24 1259a0f5d0SAkshay Belsare 1359a0f5d0SAkshay Belsare# Disable Non-Standard Crypto Algorithms 1459a0f5d0SAkshay Belsare$(call force,CFG_CRYPTO_SM2_PKE,n) 1559a0f5d0SAkshay Belsare$(call force,CFG_CRYPTO_SM2_DSA,n) 1659a0f5d0SAkshay Belsare$(call force,CFG_CRYPTO_SM2_KEP,n) 1759a0f5d0SAkshay Belsare$(call force,CFG_CRYPTO_SM3,n) 1859a0f5d0SAkshay Belsare$(call force,CFG_CRYPTO_SM4,n) 1959a0f5d0SAkshay Belsare 2059a0f5d0SAkshay Belsare# platform does not support paging; explicitly disable CFG_WITH_PAGER 2159a0f5d0SAkshay Belsare$(call force,CFG_WITH_PAGER,n) 2259a0f5d0SAkshay Belsare 2359a0f5d0SAkshay Belsare# Platform specific configurations 2459a0f5d0SAkshay Belsare$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 2559a0f5d0SAkshay Belsare$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 2659a0f5d0SAkshay Belsare$(call force,CFG_TEE_CORE_NB_CORE,8) 2759a0f5d0SAkshay Belsare$(call force,CFG_ARM_GICV3,y) 2859a0f5d0SAkshay Belsare$(call force,CFG_PL011,y) 2959a0f5d0SAkshay Belsare$(call force,CFG_GIC,y) 30d3c37848SAkshay Belsare$(call force,CFG_DT,y) 3159a0f5d0SAkshay Belsare 3259a0f5d0SAkshay BelsareCFG_CORE_RESERVED_SHM ?= n 3359a0f5d0SAkshay BelsareCFG_CORE_DYN_SHM ?= y 3459a0f5d0SAkshay BelsareCFG_WITH_STATS ?= y 3559a0f5d0SAkshay BelsareCFG_ARM64_core ?= y 36*847ee293SAkshay BelsareCFG_AUTO_MAX_PA_BITS ?= y 3759a0f5d0SAkshay Belsare 3859a0f5d0SAkshay Belsare# Enable ARM Crypto Extensions(CE) 3971aed2dbSAmey Avinash RaghatateCFG_CRYPTO_WITH_CE ?= y 4059a0f5d0SAkshay Belsare 4159a0f5d0SAkshay Belsare# Define the number of cores per cluster used in calculating core position. 4259a0f5d0SAkshay Belsare# The cluster number is shifted by this value and added to the core ID, 4359a0f5d0SAkshay Belsare# so its value represents log2(cores/cluster). 4459a0f5d0SAkshay Belsare# For AMD Versal Gen 2 there are 4 clusters and 2 cores per cluster. 4559a0f5d0SAkshay Belsare$(call force,CFG_CORE_CLUSTER_SHIFT,1) 4659a0f5d0SAkshay Belsare 4759a0f5d0SAkshay Belsare# By default optee_os is located at the following location. 4859a0f5d0SAkshay Belsare# This range to contain optee_os, TEE RAM and TA RAM. 4959a0f5d0SAkshay Belsare# Default size is 128MB. 5059a0f5d0SAkshay BelsareCFG_TZDRAM_START ?= 0x1800000 5159a0f5d0SAkshay BelsareCFG_TZDRAM_SIZE ?= 0x8000000 5259a0f5d0SAkshay Belsare 53002bd204SAmey Avinash Raghatate# Maximum size of the Device Tree Blob to accommodate 54002bd204SAmey Avinash Raghatate# device tree with additional nodes. 55002bd204SAmey Avinash RaghatateCFG_DTB_MAX_SIZE ?= 0x200000 56002bd204SAmey Avinash Raghatate 5779ea7b0aSAkshay Belsare# Console selection 5879ea7b0aSAkshay Belsare# 0 : UART0[pl011, pl011_0] (default) 5979ea7b0aSAkshay Belsare# 1 : UART1[pl011_1] 6079ea7b0aSAkshay BelsareCFG_CONSOLE_UART ?= 0 6179ea7b0aSAkshay Belsare 62d3c37848SAkshay Belsare# PS GPIO Controller configuration. 63d3c37848SAkshay BelsareCFG_AMD_PS_GPIO ?= n 64d3c37848SAkshay Belsare 65d3c37848SAkshay Belsareifeq ($(CFG_AMD_PS_GPIO),y) 66d3c37848SAkshay Belsare$(call force,CFG_MAP_EXT_DT_SECURE,y) 67d3c37848SAkshay Belsare$(call force,CFG_DRIVERS_GPIO,y) 68d3c37848SAkshay Belsareendif 69d3c37848SAkshay Belsare 7059a0f5d0SAkshay BelsareCFG_CORE_HEAP_SIZE ?= 262144 71