1PLATFORM_FLAVOR ?= generic 2 3include core/arch/arm/cpu/cortex-armv8-0.mk 4 5CFG_MMAP_REGIONS ?= 24 6 7$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 8$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 9$(call force,CFG_TEE_CORE_NB_CORE,2) 10$(call force,CFG_ARM_GICV3,y) 11$(call force,CFG_PL011,y) 12$(call force,CFG_GIC,y) 13 14# Disable core ASLR for two reasons: 15# 1. There is no source for ALSR seed, as TF-a does not provide a 16# DTB to OP-TEE. Hardware RNG is also not currently supported. 17# 2. Xilinx's bootgen can't find the OP-TEE entry point from the TEE.elf file 18# used to generate boot.bin. Enabling ASLR requires an update to TF-A. 19$(call force,CFG_CORE_ASLR,n) 20 21CFG_CRYPTO_WITH_CE ?= y 22CFG_CORE_DYN_SHM ?= y 23CFG_WITH_STATS ?= y 24CFG_ARM64_core ?= y 25 26CFG_TZDRAM_START ?= 0x60000000 27CFG_TZDRAM_SIZE ?= 0x10000000 28CFG_SHMEM_START ?= 0x70000000 29CFG_SHMEM_SIZE ?= 0x10000000 30 31ifeq ($(CFG_ARM64_core),y) 32$(call force,CFG_CORE_ARM64_PA_BITS,43) 33else 34$(call force,CFG_ARM32_core,y) 35endif 36 37# GPIO 38CFG_VERSAL_GPIO ?= y 39 40# Debug information 41CFG_VERSAL_TRACE_MBOX ?= n 42CFG_VERSAL_TRACE_PLM ?= n 43 44$(call force, CFG_VERSAL_MBOX,y) 45 46# MBOX configuration 47CFG_VERSAL_MBOX_IPI_ID ?= 3 48 49$(call force, CFG_VERSAL_RNG_DRV,y) 50$(call force, CFG_WITH_SOFTWARE_PRNG,n) 51 52# TRNG configuration 53CFG_VERSAL_TRNG_SEED_LIFE ?= 3 54CFG_VERSAL_TRNG_DF_MUL ?= 2 55 56# eFuse and BBRAM driver 57$(call force, CFG_VERSAL_NVM,y) 58 59# Crypto driver 60$(call force,CFG_CRYPTO_DRIVER,y) 61CFG_CRYPTO_DRIVER_DEBUG ?= 0 62 63CFG_VERSAL_CRYPTO_DRIVER ?= y 64 65# SHA3-384 crypto engine 66CFG_VERSAL_SHA3_384 ?= y 67