1PLATFORM_FLAVOR ?= generic 2 3include core/arch/arm/cpu/cortex-armv8-0.mk 4 5$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 6$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 7$(call force,CFG_TEE_CORE_NB_CORE,2) 8$(call force,CFG_ARM_GICV3,y) 9$(call force,CFG_PL011,y) 10$(call force,CFG_GIC,y) 11 12# Disable core ASLR for two reasons: 13# 1. There is no source for ALSR seed, as TF-a does not provide a 14# DTB to OP-TEE. Hardware RNG is also not currently supported. 15# 2. Xilinx's bootgen can't find the OP-TEE entry point from the TEE.elf file 16# used to generate boot.bin. Enabling ASLR requires an update to TF-A. 17$(call force,CFG_CORE_ASLR,n) 18 19CFG_CRYPTO_WITH_CE ?= y 20CFG_CORE_DYN_SHM ?= y 21CFG_WITH_STATS ?= y 22CFG_ARM64_core ?= y 23 24CFG_TZDRAM_START ?= 0x60000000 25CFG_TZDRAM_SIZE ?= 0x10000000 26CFG_SHMEM_START ?= 0x70000000 27CFG_SHMEM_SIZE ?= 0x10000000 28 29ifeq ($(CFG_ARM64_core),y) 30$(call force,CFG_CORE_ARM64_PA_BITS,43) 31else 32$(call force,CFG_ARM32_core,y) 33endif 34