1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2021, Arm Limited. All rights reserved. 4 */ 5 6 #include <arm.h> 7 #include <console.h> 8 #include <drivers/gic.h> 9 #include <drivers/pl011.h> 10 #include <initcall.h> 11 #include <kernel/boot.h> 12 #include <kernel/interrupt.h> 13 #include <kernel/misc.h> 14 #include <kernel/panic.h> 15 16 #include <mm/core_mmu.h> 17 #include <platform_config.h> 18 19 #ifndef CFG_CORE_SEL2_SPMC 20 static struct gic_data gic_data __nex_bss; 21 #endif 22 static struct pl011_data console_data __nex_bss; 23 24 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 25 #ifndef CFG_CORE_SEL2_SPMC 26 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 27 #endif 28 29 register_ddr(DRAM0_BASE, DRAM0_SIZE); 30 31 #ifndef CFG_CORE_SEL2_SPMC 32 void main_init_gic(void) 33 { 34 vaddr_t gicc_base; 35 36 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 37 MEM_AREA_IO_SEC); 38 if (!gicc_base) 39 panic(); 40 41 /* 42 * On ARMv8, GIC configuration is initialized in ARM-TF 43 * gicd base address is same as gicc_base. 44 */ 45 gic_init_base_addr(&gic_data, gicc_base, gicc_base); 46 itr_init(&gic_data.chip); 47 } 48 #endif 49 50 void itr_core_handler(void) 51 { 52 #ifdef CFG_CORE_SEL2_SPMC 53 panic("Secure interrupt handler not defined"); 54 #else 55 gic_it_handle(&gic_data); 56 #endif 57 } 58 59 void console_init(void) 60 { 61 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 62 CONSOLE_UART_BAUDRATE); 63 register_serial_console(&console_data.chip); 64 } 65