1 /* 2 * Copyright (c) 2015, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <platform_config.h> 29 30 #include <stdint.h> 31 #include <string.h> 32 #include <assert.h> 33 #include <drivers/gic.h> 34 #include <drivers/serial8250_uart.h> 35 #include <arm.h> 36 #include <kernel/generic_boot.h> 37 #include <kernel/panic.h> 38 #include <kernel/pm_stubs.h> 39 #include <trace.h> 40 #include <kernel/misc.h> 41 #include <kernel/mutex.h> 42 #include <kernel/tee_time.h> 43 #include <mm/core_mmu.h> 44 #include <tee/entry_std.h> 45 #include <tee/entry_fast.h> 46 #include <console.h> 47 #include <sm/sm.h> 48 49 static void main_fiq(void); 50 51 static const struct thread_handlers handlers = { 52 .std_smc = tee_entry_std, 53 .fast_smc = tee_entry_fast, 54 .fiq = main_fiq, 55 .cpu_on = pm_panic, 56 .cpu_off = pm_panic, 57 .cpu_suspend = pm_panic, 58 .cpu_resume = pm_panic, 59 .system_off = pm_panic, 60 .system_reset = pm_panic, 61 }; 62 63 const struct thread_handlers *generic_boot_get_handlers(void) 64 { 65 return &handlers; 66 } 67 68 static void main_fiq(void) 69 { 70 panic(); 71 } 72 73 void console_init(void) 74 { 75 serial8250_uart_init(CONSOLE_UART_BASE, 76 CONSOLE_UART_CLK_IN_HZ, 77 CONSOLE_BAUDRATE); 78 } 79 80 void console_putc(int ch) 81 { 82 serial8250_uart_putc(ch, CONSOLE_UART_BASE); 83 if (ch == '\n') 84 serial8250_uart_putc('\r', CONSOLE_UART_BASE); 85 } 86 87 void console_flush(void) 88 { 89 serial8250_uart_flush_tx_fifo(CONSOLE_UART_BASE); 90 } 91 92 struct plat_nsec_ctx { 93 uint32_t usr_sp; 94 uint32_t usr_lr; 95 uint32_t svc_sp; 96 uint32_t svc_lr; 97 uint32_t svc_spsr; 98 uint32_t abt_sp; 99 uint32_t abt_lr; 100 uint32_t abt_spsr; 101 uint32_t und_sp; 102 uint32_t und_lr; 103 uint32_t und_spsr; 104 uint32_t irq_sp; 105 uint32_t irq_lr; 106 uint32_t irq_spsr; 107 uint32_t fiq_sp; 108 uint32_t fiq_lr; 109 uint32_t fiq_spsr; 110 uint32_t fiq_rx[5]; 111 uint32_t mon_lr; 112 uint32_t mon_spsr; 113 }; 114 115 void init_sec_mon(uint32_t nsec_entry) 116 { 117 struct plat_nsec_ctx *plat_ctx = (struct plat_nsec_ctx *)nsec_entry; 118 struct sm_nsec_ctx *nsec_ctx; 119 120 /* Invalidate cache to fetch data from external memory */ 121 cache_maintenance_l1(DCACHE_AREA_INVALIDATE, (void *)nsec_entry, 122 sizeof(struct plat_nsec_ctx)); 123 124 /* Initialize secure monitor */ 125 nsec_ctx = sm_get_nsec_ctx(); 126 127 nsec_ctx->usr_sp = plat_ctx->usr_sp; 128 nsec_ctx->usr_lr = plat_ctx->usr_lr; 129 nsec_ctx->irq_spsr = plat_ctx->irq_spsr; 130 nsec_ctx->irq_sp = plat_ctx->irq_sp; 131 nsec_ctx->irq_lr = plat_ctx->irq_lr; 132 nsec_ctx->svc_spsr = plat_ctx->svc_spsr; 133 nsec_ctx->svc_sp = plat_ctx->svc_sp; 134 nsec_ctx->svc_lr = plat_ctx->svc_lr; 135 nsec_ctx->abt_spsr = plat_ctx->abt_spsr; 136 nsec_ctx->abt_sp = plat_ctx->abt_sp; 137 nsec_ctx->abt_lr = plat_ctx->abt_lr; 138 nsec_ctx->und_spsr = plat_ctx->und_spsr; 139 nsec_ctx->und_sp = plat_ctx->und_sp; 140 nsec_ctx->und_lr = plat_ctx->und_lr; 141 nsec_ctx->mon_lr = plat_ctx->mon_lr; 142 nsec_ctx->mon_spsr = plat_ctx->mon_spsr; 143 } 144 145 146