1 /* 2 * Copyright (c) 2015, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <platform_config.h> 29 30 #include <stdint.h> 31 #include <string.h> 32 #include <assert.h> 33 #include <drivers/gic.h> 34 #include <drivers/serial8250_uart.h> 35 #include <arm.h> 36 #include <kernel/generic_boot.h> 37 #include <kernel/panic.h> 38 #include <kernel/pm_stubs.h> 39 #include <trace.h> 40 #include <kernel/misc.h> 41 #include <kernel/mutex.h> 42 #include <kernel/tee_time.h> 43 #include <mm/core_mmu.h> 44 #include <mm/core_memprot.h> 45 #include <tee/entry_std.h> 46 #include <tee/entry_fast.h> 47 #include <console.h> 48 #include <sm/sm.h> 49 50 static void main_fiq(void); 51 52 static const struct thread_handlers handlers = { 53 .std_smc = tee_entry_std, 54 .fast_smc = tee_entry_fast, 55 .fiq = main_fiq, 56 .cpu_on = pm_panic, 57 .cpu_off = pm_panic, 58 .cpu_suspend = pm_panic, 59 .cpu_resume = pm_panic, 60 .system_off = pm_panic, 61 .system_reset = pm_panic, 62 }; 63 64 const struct thread_handlers *generic_boot_get_handlers(void) 65 { 66 return &handlers; 67 } 68 69 static void main_fiq(void) 70 { 71 panic(); 72 } 73 74 static vaddr_t console_base(void) 75 { 76 static void *va; 77 78 if (cpu_mmu_enabled()) { 79 if (!va) 80 va = phys_to_virt(CONSOLE_UART_BASE, MEM_AREA_IO_SEC); 81 return (vaddr_t)va; 82 } 83 return CONSOLE_UART_BASE; 84 } 85 86 void console_init(void) 87 { 88 serial8250_uart_init(console_base(), CONSOLE_UART_CLK_IN_HZ, 89 CONSOLE_BAUDRATE); 90 } 91 92 void console_putc(int ch) 93 { 94 vaddr_t base = console_base(); 95 96 if (ch == '\n') 97 serial8250_uart_putc('\r', base); 98 serial8250_uart_putc(ch, base); 99 } 100 101 void console_flush(void) 102 { 103 serial8250_uart_flush_tx_fifo(console_base()); 104 } 105 106 107 108 struct plat_nsec_ctx { 109 uint32_t usr_sp; 110 uint32_t usr_lr; 111 uint32_t svc_sp; 112 uint32_t svc_lr; 113 uint32_t svc_spsr; 114 uint32_t abt_sp; 115 uint32_t abt_lr; 116 uint32_t abt_spsr; 117 uint32_t und_sp; 118 uint32_t und_lr; 119 uint32_t und_spsr; 120 uint32_t irq_sp; 121 uint32_t irq_lr; 122 uint32_t irq_spsr; 123 uint32_t fiq_sp; 124 uint32_t fiq_lr; 125 uint32_t fiq_spsr; 126 uint32_t fiq_rx[5]; 127 uint32_t mon_lr; 128 uint32_t mon_spsr; 129 }; 130 131 void init_sec_mon(unsigned long nsec_entry) 132 { 133 struct plat_nsec_ctx *plat_ctx = (struct plat_nsec_ctx *)nsec_entry; 134 struct sm_nsec_ctx *nsec_ctx; 135 136 /* Invalidate cache to fetch data from external memory */ 137 cache_maintenance_l1(DCACHE_AREA_INVALIDATE, (void *)nsec_entry, 138 sizeof(struct plat_nsec_ctx)); 139 140 /* Initialize secure monitor */ 141 nsec_ctx = sm_get_nsec_ctx(); 142 143 nsec_ctx->usr_sp = plat_ctx->usr_sp; 144 nsec_ctx->usr_lr = plat_ctx->usr_lr; 145 nsec_ctx->irq_spsr = plat_ctx->irq_spsr; 146 nsec_ctx->irq_sp = plat_ctx->irq_sp; 147 nsec_ctx->irq_lr = plat_ctx->irq_lr; 148 nsec_ctx->svc_spsr = plat_ctx->svc_spsr; 149 nsec_ctx->svc_sp = plat_ctx->svc_sp; 150 nsec_ctx->svc_lr = plat_ctx->svc_lr; 151 nsec_ctx->abt_spsr = plat_ctx->abt_spsr; 152 nsec_ctx->abt_sp = plat_ctx->abt_sp; 153 nsec_ctx->abt_lr = plat_ctx->abt_lr; 154 nsec_ctx->und_spsr = plat_ctx->und_spsr; 155 nsec_ctx->und_sp = plat_ctx->und_sp; 156 nsec_ctx->und_lr = plat_ctx->und_lr; 157 nsec_ctx->mon_lr = plat_ctx->mon_lr; 158 nsec_ctx->mon_spsr = plat_ctx->mon_spsr; 159 } 160 161 162