1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 6 #include <arm.h> 7 #include <assert.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/serial8250_uart.h> 11 #include <kernel/boot.h> 12 #include <kernel/interrupt.h> 13 #include <kernel/misc.h> 14 #include <kernel/mutex.h> 15 #include <kernel/panic.h> 16 #include <kernel/tee_common_otp.h> 17 #include <kernel/tee_time.h> 18 #include <mm/core_memprot.h> 19 #include <mm/core_mmu.h> 20 #include <platform_config.h> 21 #include <sm/sm.h> 22 #include <stdint.h> 23 #include <string.h> 24 #include <trace.h> 25 26 #define PLAT_HW_UNIQUE_KEY_LENGTH 32 27 28 static struct gic_data gic_data; 29 static struct serial8250_uart_data console_data; 30 static uint8_t plat_huk[PLAT_HW_UNIQUE_KEY_LENGTH]; 31 32 register_phys_mem(MEM_AREA_RAM_SEC, TZDRAM_BASE, TEE_RAM_VA_SIZE); 33 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GICC_SIZE); 35 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GICD_SIZE); 36 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 37 SERIAL8250_UART_REG_SIZE); 38 39 void main_init_gic(void) 40 { 41 gic_init(&gic_data, GICC_BASE, GICD_BASE); 42 itr_init(&gic_data.chip); 43 } 44 45 void main_secondary_init_gic(void) 46 { 47 gic_cpu_init(&gic_data); 48 } 49 50 void itr_core_handler(void) 51 { 52 gic_it_handle(&gic_data); 53 } 54 55 struct plat_nsec_ctx { 56 uint32_t usr_sp; 57 uint32_t usr_lr; 58 uint32_t svc_sp; 59 uint32_t svc_lr; 60 uint32_t svc_spsr; 61 uint32_t abt_sp; 62 uint32_t abt_lr; 63 uint32_t abt_spsr; 64 uint32_t und_sp; 65 uint32_t und_lr; 66 uint32_t und_spsr; 67 uint32_t irq_sp; 68 uint32_t irq_lr; 69 uint32_t irq_spsr; 70 uint32_t fiq_sp; 71 uint32_t fiq_lr; 72 uint32_t fiq_spsr; 73 uint32_t fiq_rx[5]; 74 uint32_t mon_lr; 75 uint32_t mon_spsr; 76 }; 77 78 struct plat_boot_args { 79 struct plat_nsec_ctx nsec_ctx; 80 uint8_t huk[PLAT_HW_UNIQUE_KEY_LENGTH]; 81 }; 82 83 void init_sec_mon(unsigned long nsec_entry) 84 { 85 struct plat_boot_args *plat_boot_args; 86 struct sm_nsec_ctx *nsec_ctx; 87 88 plat_boot_args = phys_to_virt(nsec_entry, MEM_AREA_IO_SEC, 1); 89 if (!plat_boot_args) 90 panic(); 91 92 /* Invalidate cache to fetch data from external memory */ 93 cache_op_inner(DCACHE_AREA_INVALIDATE, 94 plat_boot_args, sizeof(*plat_boot_args)); 95 96 /* Initialize secure monitor */ 97 nsec_ctx = sm_get_nsec_ctx(); 98 99 nsec_ctx->ub_regs.usr_sp = plat_boot_args->nsec_ctx.usr_sp; 100 nsec_ctx->ub_regs.usr_lr = plat_boot_args->nsec_ctx.usr_lr; 101 nsec_ctx->ub_regs.irq_spsr = plat_boot_args->nsec_ctx.irq_spsr; 102 nsec_ctx->ub_regs.irq_sp = plat_boot_args->nsec_ctx.irq_sp; 103 nsec_ctx->ub_regs.irq_lr = plat_boot_args->nsec_ctx.irq_lr; 104 nsec_ctx->ub_regs.svc_spsr = plat_boot_args->nsec_ctx.svc_spsr; 105 nsec_ctx->ub_regs.svc_sp = plat_boot_args->nsec_ctx.svc_sp; 106 nsec_ctx->ub_regs.svc_lr = plat_boot_args->nsec_ctx.svc_lr; 107 nsec_ctx->ub_regs.abt_spsr = plat_boot_args->nsec_ctx.abt_spsr; 108 nsec_ctx->ub_regs.abt_sp = plat_boot_args->nsec_ctx.abt_sp; 109 nsec_ctx->ub_regs.abt_lr = plat_boot_args->nsec_ctx.abt_lr; 110 nsec_ctx->ub_regs.und_spsr = plat_boot_args->nsec_ctx.und_spsr; 111 nsec_ctx->ub_regs.und_sp = plat_boot_args->nsec_ctx.und_sp; 112 nsec_ctx->ub_regs.und_lr = plat_boot_args->nsec_ctx.und_lr; 113 nsec_ctx->mon_lr = plat_boot_args->nsec_ctx.mon_lr; 114 nsec_ctx->mon_spsr = plat_boot_args->nsec_ctx.mon_spsr; 115 116 memcpy(plat_huk, plat_boot_args->huk, sizeof(plat_boot_args->huk)); 117 } 118 119 void console_init(void) 120 { 121 serial8250_uart_init(&console_data, CONSOLE_UART_BASE, 122 CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE); 123 register_serial_console(&console_data.chip); 124 } 125 126 #if defined(CFG_OTP_SUPPORT) 127 128 TEE_Result tee_otp_get_hw_unique_key(struct tee_hw_unique_key *hwkey) 129 { 130 memcpy(&hwkey->data[0], &plat_huk[0], sizeof(hwkey->data)); 131 return TEE_SUCCESS; 132 } 133 134 #endif 135