xref: /optee_os/core/arch/arm/plat-ti/main.c (revision 82c9f5974071a8d8f64af8e8ec7e0e45c1d3b472)
1 /*
2  * Copyright (c) 2015, Linaro Limited
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  * this list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form must reproduce the above copyright notice,
12  * this list of conditions and the following disclaimer in the documentation
13  * and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
19  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25  * POSSIBILITY OF SUCH DAMAGE.
26  */
27 
28 #include <platform_config.h>
29 
30 #include <stdint.h>
31 #include <string.h>
32 #include <assert.h>
33 #include <drivers/gic.h>
34 #include <arm.h>
35 #include <kernel/generic_boot.h>
36 #include <kernel/panic.h>
37 #include <kernel/pm_stubs.h>
38 #include <trace.h>
39 #include <kernel/misc.h>
40 #include <kernel/mutex.h>
41 #include <kernel/tee_time.h>
42 #include <mm/core_mmu.h>
43 #include <mm/core_memprot.h>
44 #include <tee/entry_std.h>
45 #include <tee/entry_fast.h>
46 #include <console.h>
47 #include <sm/sm.h>
48 
49 static void main_fiq(void)
50 {
51 	panic();
52 }
53 
54 static const struct thread_handlers handlers = {
55 	.std_smc = tee_entry_std,
56 	.fast_smc = tee_entry_fast,
57 	.fiq = main_fiq,
58 	.cpu_on = pm_panic,
59 	.cpu_off = pm_panic,
60 	.cpu_suspend = pm_panic,
61 	.cpu_resume = pm_panic,
62 	.system_off = pm_panic,
63 	.system_reset = pm_panic,
64 };
65 
66 const struct thread_handlers *generic_boot_get_handlers(void)
67 {
68 	return &handlers;
69 }
70 
71 struct plat_nsec_ctx {
72 	uint32_t usr_sp;
73 	uint32_t usr_lr;
74 	uint32_t svc_sp;
75 	uint32_t svc_lr;
76 	uint32_t svc_spsr;
77 	uint32_t abt_sp;
78 	uint32_t abt_lr;
79 	uint32_t abt_spsr;
80 	uint32_t und_sp;
81 	uint32_t und_lr;
82 	uint32_t und_spsr;
83 	uint32_t irq_sp;
84 	uint32_t irq_lr;
85 	uint32_t irq_spsr;
86 	uint32_t fiq_sp;
87 	uint32_t fiq_lr;
88 	uint32_t fiq_spsr;
89 	uint32_t fiq_rx[5];
90 	uint32_t mon_lr;
91 	uint32_t mon_spsr;
92 };
93 
94 void init_sec_mon(unsigned long nsec_entry)
95 {
96 	struct plat_nsec_ctx *plat_ctx;
97 	struct sm_nsec_ctx *nsec_ctx;
98 
99 	plat_ctx = phys_to_virt(nsec_entry, MEM_AREA_IO_SEC);
100 	if (!plat_ctx)
101 		panic();
102 
103 	/* Invalidate cache to fetch data from external memory */
104 	cache_maintenance_l1(DCACHE_AREA_INVALIDATE,
105 			     plat_ctx, sizeof(*plat_ctx));
106 
107 	/* Initialize secure monitor */
108 	nsec_ctx = sm_get_nsec_ctx();
109 
110 	nsec_ctx->mode_regs.usr_sp = plat_ctx->usr_sp;
111 	nsec_ctx->mode_regs.usr_lr = plat_ctx->usr_lr;
112 	nsec_ctx->mode_regs.irq_spsr = plat_ctx->irq_spsr;
113 	nsec_ctx->mode_regs.irq_sp = plat_ctx->irq_sp;
114 	nsec_ctx->mode_regs.irq_lr = plat_ctx->irq_lr;
115 	nsec_ctx->mode_regs.svc_spsr = plat_ctx->svc_spsr;
116 	nsec_ctx->mode_regs.svc_sp = plat_ctx->svc_sp;
117 	nsec_ctx->mode_regs.svc_lr = plat_ctx->svc_lr;
118 	nsec_ctx->mode_regs.abt_spsr = plat_ctx->abt_spsr;
119 	nsec_ctx->mode_regs.abt_sp = plat_ctx->abt_sp;
120 	nsec_ctx->mode_regs.abt_lr = plat_ctx->abt_lr;
121 	nsec_ctx->mode_regs.und_spsr = plat_ctx->und_spsr;
122 	nsec_ctx->mode_regs.und_sp = plat_ctx->und_sp;
123 	nsec_ctx->mode_regs.und_lr = plat_ctx->und_lr;
124 	nsec_ctx->mon_lr = plat_ctx->mon_lr;
125 	nsec_ctx->mon_spsr = plat_ctx->mon_spsr;
126 }
127