1 /* 2 * Copyright (c) 2015, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <platform_config.h> 29 30 #include <stdint.h> 31 #include <string.h> 32 #include <assert.h> 33 #include <drivers/gic.h> 34 #include <arm.h> 35 #include <kernel/generic_boot.h> 36 #include <kernel/panic.h> 37 #include <kernel/pm_stubs.h> 38 #include <trace.h> 39 #include <kernel/misc.h> 40 #include <kernel/mutex.h> 41 #include <kernel/tee_time.h> 42 #include <mm/core_mmu.h> 43 #include <mm/core_memprot.h> 44 #include <tee/entry_std.h> 45 #include <tee/entry_fast.h> 46 #include <console.h> 47 #include <sm/sm.h> 48 49 static struct gic_data gic_data; 50 51 register_phys_mem(MEM_AREA_IO_SEC, GICC_BASE, GICC_SIZE); 52 register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, GICD_SIZE); 53 54 void main_init_gic(void) 55 { 56 vaddr_t gicc_base; 57 vaddr_t gicd_base; 58 59 gicc_base = (vaddr_t)phys_to_virt(GICC_BASE, MEM_AREA_IO_SEC); 60 gicd_base = (vaddr_t)phys_to_virt(GICD_BASE, MEM_AREA_IO_SEC); 61 62 if (!gicc_base || !gicd_base) 63 panic(); 64 65 gic_init(&gic_data, gicc_base, gicd_base); 66 itr_init(&gic_data.chip); 67 } 68 69 void main_secondary_init_gic(void) 70 { 71 gic_cpu_init(&gic_data); 72 } 73 74 static void main_fiq(void) 75 { 76 gic_it_handle(&gic_data); 77 } 78 79 static const struct thread_handlers handlers = { 80 .std_smc = tee_entry_std, 81 .fast_smc = tee_entry_fast, 82 .nintr = main_fiq, 83 .cpu_on = pm_panic, 84 .cpu_off = pm_panic, 85 .cpu_suspend = pm_panic, 86 .cpu_resume = pm_panic, 87 .system_off = pm_panic, 88 .system_reset = pm_panic, 89 }; 90 91 const struct thread_handlers *generic_boot_get_handlers(void) 92 { 93 return &handlers; 94 } 95 96 struct plat_nsec_ctx { 97 uint32_t usr_sp; 98 uint32_t usr_lr; 99 uint32_t svc_sp; 100 uint32_t svc_lr; 101 uint32_t svc_spsr; 102 uint32_t abt_sp; 103 uint32_t abt_lr; 104 uint32_t abt_spsr; 105 uint32_t und_sp; 106 uint32_t und_lr; 107 uint32_t und_spsr; 108 uint32_t irq_sp; 109 uint32_t irq_lr; 110 uint32_t irq_spsr; 111 uint32_t fiq_sp; 112 uint32_t fiq_lr; 113 uint32_t fiq_spsr; 114 uint32_t fiq_rx[5]; 115 uint32_t mon_lr; 116 uint32_t mon_spsr; 117 }; 118 119 void init_sec_mon(unsigned long nsec_entry) 120 { 121 struct plat_nsec_ctx *plat_ctx; 122 struct sm_nsec_ctx *nsec_ctx; 123 124 plat_ctx = phys_to_virt(nsec_entry, MEM_AREA_IO_SEC); 125 if (!plat_ctx) 126 panic(); 127 128 /* Invalidate cache to fetch data from external memory */ 129 cache_maintenance_l1(DCACHE_AREA_INVALIDATE, 130 plat_ctx, sizeof(*plat_ctx)); 131 132 /* Initialize secure monitor */ 133 nsec_ctx = sm_get_nsec_ctx(); 134 135 nsec_ctx->mode_regs.usr_sp = plat_ctx->usr_sp; 136 nsec_ctx->mode_regs.usr_lr = plat_ctx->usr_lr; 137 nsec_ctx->mode_regs.irq_spsr = plat_ctx->irq_spsr; 138 nsec_ctx->mode_regs.irq_sp = plat_ctx->irq_sp; 139 nsec_ctx->mode_regs.irq_lr = plat_ctx->irq_lr; 140 nsec_ctx->mode_regs.svc_spsr = plat_ctx->svc_spsr; 141 nsec_ctx->mode_regs.svc_sp = plat_ctx->svc_sp; 142 nsec_ctx->mode_regs.svc_lr = plat_ctx->svc_lr; 143 nsec_ctx->mode_regs.abt_spsr = plat_ctx->abt_spsr; 144 nsec_ctx->mode_regs.abt_sp = plat_ctx->abt_sp; 145 nsec_ctx->mode_regs.abt_lr = plat_ctx->abt_lr; 146 nsec_ctx->mode_regs.und_spsr = plat_ctx->und_spsr; 147 nsec_ctx->mode_regs.und_sp = plat_ctx->und_sp; 148 nsec_ctx->mode_regs.und_lr = plat_ctx->und_lr; 149 nsec_ctx->mon_lr = plat_ctx->mon_lr; 150 nsec_ctx->mon_spsr = plat_ctx->mon_spsr; 151 } 152