1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 6 #include <arm.h> 7 #include <assert.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/serial8250_uart.h> 11 #include <kernel/boot.h> 12 #include <kernel/interrupt.h> 13 #include <kernel/misc.h> 14 #include <kernel/mutex.h> 15 #include <kernel/panic.h> 16 #include <kernel/tee_common_otp.h> 17 #include <kernel/tee_time.h> 18 #include <mm/core_memprot.h> 19 #include <mm/core_mmu.h> 20 #include <platform_config.h> 21 #include <sm/sm.h> 22 #include <stdint.h> 23 #include <string.h> 24 #include <trace.h> 25 26 #define PLAT_HW_UNIQUE_KEY_LENGTH 32 27 28 static struct gic_data gic_data; 29 static struct serial8250_uart_data console_data; 30 static uint8_t plat_huk[PLAT_HW_UNIQUE_KEY_LENGTH]; 31 32 register_phys_mem(MEM_AREA_RAM_SEC, TZDRAM_BASE, TEE_RAM_VA_SIZE); 33 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GICC_SIZE); 35 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GICD_SIZE); 36 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 37 SERIAL8250_UART_REG_SIZE); 38 39 void main_init_gic(void) 40 { 41 vaddr_t gicc_base; 42 vaddr_t gicd_base; 43 44 gicc_base = (vaddr_t)phys_to_virt(GICC_BASE, MEM_AREA_IO_SEC, 45 GICC_SIZE); 46 gicd_base = (vaddr_t)phys_to_virt(GICD_BASE, MEM_AREA_IO_SEC, 47 GICD_SIZE); 48 if (!gicc_base || !gicd_base) 49 panic(); 50 51 gic_init(&gic_data, gicc_base, gicd_base); 52 itr_init(&gic_data.chip); 53 } 54 55 void main_secondary_init_gic(void) 56 { 57 gic_cpu_init(&gic_data); 58 } 59 60 void itr_core_handler(void) 61 { 62 gic_it_handle(&gic_data); 63 } 64 65 struct plat_nsec_ctx { 66 uint32_t usr_sp; 67 uint32_t usr_lr; 68 uint32_t svc_sp; 69 uint32_t svc_lr; 70 uint32_t svc_spsr; 71 uint32_t abt_sp; 72 uint32_t abt_lr; 73 uint32_t abt_spsr; 74 uint32_t und_sp; 75 uint32_t und_lr; 76 uint32_t und_spsr; 77 uint32_t irq_sp; 78 uint32_t irq_lr; 79 uint32_t irq_spsr; 80 uint32_t fiq_sp; 81 uint32_t fiq_lr; 82 uint32_t fiq_spsr; 83 uint32_t fiq_rx[5]; 84 uint32_t mon_lr; 85 uint32_t mon_spsr; 86 }; 87 88 struct plat_boot_args { 89 struct plat_nsec_ctx nsec_ctx; 90 uint8_t huk[PLAT_HW_UNIQUE_KEY_LENGTH]; 91 }; 92 93 void init_sec_mon(unsigned long nsec_entry) 94 { 95 struct plat_boot_args *plat_boot_args; 96 struct sm_nsec_ctx *nsec_ctx; 97 98 plat_boot_args = phys_to_virt(nsec_entry, MEM_AREA_IO_SEC, 1); 99 if (!plat_boot_args) 100 panic(); 101 102 /* Invalidate cache to fetch data from external memory */ 103 cache_op_inner(DCACHE_AREA_INVALIDATE, 104 plat_boot_args, sizeof(*plat_boot_args)); 105 106 /* Initialize secure monitor */ 107 nsec_ctx = sm_get_nsec_ctx(); 108 109 nsec_ctx->ub_regs.usr_sp = plat_boot_args->nsec_ctx.usr_sp; 110 nsec_ctx->ub_regs.usr_lr = plat_boot_args->nsec_ctx.usr_lr; 111 nsec_ctx->ub_regs.irq_spsr = plat_boot_args->nsec_ctx.irq_spsr; 112 nsec_ctx->ub_regs.irq_sp = plat_boot_args->nsec_ctx.irq_sp; 113 nsec_ctx->ub_regs.irq_lr = plat_boot_args->nsec_ctx.irq_lr; 114 nsec_ctx->ub_regs.svc_spsr = plat_boot_args->nsec_ctx.svc_spsr; 115 nsec_ctx->ub_regs.svc_sp = plat_boot_args->nsec_ctx.svc_sp; 116 nsec_ctx->ub_regs.svc_lr = plat_boot_args->nsec_ctx.svc_lr; 117 nsec_ctx->ub_regs.abt_spsr = plat_boot_args->nsec_ctx.abt_spsr; 118 nsec_ctx->ub_regs.abt_sp = plat_boot_args->nsec_ctx.abt_sp; 119 nsec_ctx->ub_regs.abt_lr = plat_boot_args->nsec_ctx.abt_lr; 120 nsec_ctx->ub_regs.und_spsr = plat_boot_args->nsec_ctx.und_spsr; 121 nsec_ctx->ub_regs.und_sp = plat_boot_args->nsec_ctx.und_sp; 122 nsec_ctx->ub_regs.und_lr = plat_boot_args->nsec_ctx.und_lr; 123 nsec_ctx->mon_lr = plat_boot_args->nsec_ctx.mon_lr; 124 nsec_ctx->mon_spsr = plat_boot_args->nsec_ctx.mon_spsr; 125 126 memcpy(plat_huk, plat_boot_args->huk, sizeof(plat_boot_args->huk)); 127 } 128 129 void console_init(void) 130 { 131 serial8250_uart_init(&console_data, CONSOLE_UART_BASE, 132 CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE); 133 register_serial_console(&console_data.chip); 134 } 135 136 #if defined(CFG_OTP_SUPPORT) 137 138 TEE_Result tee_otp_get_hw_unique_key(struct tee_hw_unique_key *hwkey) 139 { 140 memcpy(&hwkey->data[0], &plat_huk[0], sizeof(hwkey->data)); 141 return TEE_SUCCESS; 142 } 143 144 #endif 145