1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 6 #include <arm.h> 7 #include <assert.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/serial8250_uart.h> 11 #include <kernel/boot.h> 12 #include <kernel/misc.h> 13 #include <kernel/mutex.h> 14 #include <kernel/panic.h> 15 #include <kernel/tee_common_otp.h> 16 #include <kernel/tee_time.h> 17 #include <mm/core_memprot.h> 18 #include <mm/core_mmu.h> 19 #include <platform_config.h> 20 #include <sm/sm.h> 21 #include <stdint.h> 22 #include <string.h> 23 #include <trace.h> 24 25 #define PLAT_HW_UNIQUE_KEY_LENGTH 32 26 27 static struct serial8250_uart_data console_data; 28 static uint8_t plat_huk[PLAT_HW_UNIQUE_KEY_LENGTH]; 29 30 register_phys_mem(MEM_AREA_RAM_SEC, TZDRAM_BASE, TEE_RAM_VA_SIZE); 31 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_SIZE); 32 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GICC_SIZE); 33 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GICD_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 35 SERIAL8250_UART_REG_SIZE); 36 37 void boot_primary_init_intc(void) 38 { 39 gic_init(GICC_BASE, GICD_BASE); 40 } 41 42 void boot_secondary_init_intc(void) 43 { 44 gic_init_per_cpu(); 45 } 46 47 struct plat_nsec_ctx { 48 uint32_t usr_sp; 49 uint32_t usr_lr; 50 uint32_t svc_sp; 51 uint32_t svc_lr; 52 uint32_t svc_spsr; 53 uint32_t abt_sp; 54 uint32_t abt_lr; 55 uint32_t abt_spsr; 56 uint32_t und_sp; 57 uint32_t und_lr; 58 uint32_t und_spsr; 59 uint32_t irq_sp; 60 uint32_t irq_lr; 61 uint32_t irq_spsr; 62 uint32_t fiq_sp; 63 uint32_t fiq_lr; 64 uint32_t fiq_spsr; 65 uint32_t fiq_rx[5]; 66 uint32_t mon_lr; 67 uint32_t mon_spsr; 68 }; 69 70 struct plat_boot_args { 71 struct plat_nsec_ctx nsec_ctx; 72 uint8_t huk[PLAT_HW_UNIQUE_KEY_LENGTH]; 73 }; 74 75 void init_sec_mon(unsigned long nsec_entry __unused) 76 { 77 struct plat_boot_args *plat_boot_args; 78 struct sm_nsec_ctx *nsec_ctx; 79 80 plat_boot_args = phys_to_virt(boot_arg_nsec_entry, MEM_AREA_IO_SEC, 1); 81 if (!plat_boot_args) 82 panic(); 83 84 /* Invalidate cache to fetch data from external memory */ 85 cache_op_inner(DCACHE_AREA_INVALIDATE, 86 plat_boot_args, sizeof(*plat_boot_args)); 87 88 /* Initialize secure monitor */ 89 nsec_ctx = sm_get_nsec_ctx(); 90 91 nsec_ctx->ub_regs.usr_sp = plat_boot_args->nsec_ctx.usr_sp; 92 nsec_ctx->ub_regs.usr_lr = plat_boot_args->nsec_ctx.usr_lr; 93 nsec_ctx->ub_regs.irq_spsr = plat_boot_args->nsec_ctx.irq_spsr; 94 nsec_ctx->ub_regs.irq_sp = plat_boot_args->nsec_ctx.irq_sp; 95 nsec_ctx->ub_regs.irq_lr = plat_boot_args->nsec_ctx.irq_lr; 96 nsec_ctx->ub_regs.svc_spsr = plat_boot_args->nsec_ctx.svc_spsr; 97 nsec_ctx->ub_regs.svc_sp = plat_boot_args->nsec_ctx.svc_sp; 98 nsec_ctx->ub_regs.svc_lr = plat_boot_args->nsec_ctx.svc_lr; 99 nsec_ctx->ub_regs.abt_spsr = plat_boot_args->nsec_ctx.abt_spsr; 100 nsec_ctx->ub_regs.abt_sp = plat_boot_args->nsec_ctx.abt_sp; 101 nsec_ctx->ub_regs.abt_lr = plat_boot_args->nsec_ctx.abt_lr; 102 nsec_ctx->ub_regs.und_spsr = plat_boot_args->nsec_ctx.und_spsr; 103 nsec_ctx->ub_regs.und_sp = plat_boot_args->nsec_ctx.und_sp; 104 nsec_ctx->ub_regs.und_lr = plat_boot_args->nsec_ctx.und_lr; 105 nsec_ctx->mon_lr = plat_boot_args->nsec_ctx.mon_lr; 106 nsec_ctx->mon_spsr = plat_boot_args->nsec_ctx.mon_spsr; 107 } 108 109 /* Early init HUK before SSK is derived by tee_fs_init_key_manager */ 110 static TEE_Result early_init_huk(void) 111 { 112 struct plat_boot_args *plat_boot_args; 113 114 plat_boot_args = phys_to_virt(boot_arg_nsec_entry, MEM_AREA_IO_SEC, 1); 115 if (!plat_boot_args) 116 panic(); 117 118 /* Invalidate cache to fetch data from external memory */ 119 cache_op_inner(DCACHE_AREA_INVALIDATE, 120 plat_boot_args, sizeof(*plat_boot_args)); 121 122 memcpy(plat_huk, plat_boot_args->huk, sizeof(plat_boot_args->huk)); 123 return TEE_SUCCESS; 124 } 125 early_init(early_init_huk); 126 127 void plat_console_init(void) 128 { 129 serial8250_uart_init(&console_data, CONSOLE_UART_BASE, 130 CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE); 131 register_serial_console(&console_data.chip); 132 } 133 134 #if defined(CFG_OTP_SUPPORT) 135 136 TEE_Result tee_otp_get_hw_unique_key(struct tee_hw_unique_key *hwkey) 137 { 138 memcpy(&hwkey->data[0], &plat_huk[0], sizeof(hwkey->data)); 139 return TEE_SUCCESS; 140 } 141 142 #endif 143