xref: /optee_os/core/arch/arm/plat-synquacer/main.c (revision 62f21181c547da3bd098908300e5699e9ae5cca9)
1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3  * Copyright (c) 2018, Linaro Limited
4  */
5 
6 #include <arm.h>
7 #include <console.h>
8 #include <drivers/gic.h>
9 #include <drivers/pl011.h>
10 #include <io.h>
11 #include <kernel/generic_boot.h>
12 #include <kernel/misc.h>
13 #include <kernel/panic.h>
14 #include <kernel/pm_stubs.h>
15 #include <kernel/thread.h>
16 #include <mm/core_memprot.h>
17 #include <platform_config.h>
18 #include <sm/optee_smc.h>
19 #include <tee/entry_fast.h>
20 #include <tee/entry_std.h>
21 
22 static void main_fiq(void);
23 
24 static const struct thread_handlers handlers = {
25 	.std_smc = tee_entry_std,
26 	.fast_smc = tee_entry_fast,
27 	.nintr = main_fiq,
28 	.cpu_on = cpu_on_handler,
29 	.cpu_off = pm_do_nothing,
30 	.cpu_suspend = pm_do_nothing,
31 	.cpu_resume = pm_do_nothing,
32 	.system_off = pm_do_nothing,
33 	.system_reset = pm_do_nothing,
34 };
35 
36 static struct gic_data gic_data;
37 static struct pl011_data console_data;
38 
39 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CORE_MMU_DEVICE_SIZE);
40 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE);
41 
42 const struct thread_handlers *generic_boot_get_handlers(void)
43 {
44 	return &handlers;
45 }
46 
47 static void main_fiq(void)
48 {
49 	panic();
50 }
51 
52 void console_init(void)
53 {
54 	pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ,
55 		   CONSOLE_BAUDRATE);
56 	register_serial_console(&console_data.chip);
57 }
58 
59 void main_init_gic(void)
60 {
61 	vaddr_t gicd_base;
62 
63 	gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET,
64 					  MEM_AREA_IO_SEC);
65 
66 	if (!gicd_base)
67 		panic();
68 
69 	/* Initialize GIC */
70 	gic_init(&gic_data, 0, gicd_base);
71 	itr_init(&gic_data.chip);
72 }
73 
74 void main_secondary_init_gic(void)
75 {
76 	gic_cpu_init(&gic_data);
77 }
78