xref: /optee_os/core/arch/arm/plat-synquacer/main.c (revision 5a913ee74d3c71af2a2860ce8a4e7aeab2916f9b)
1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3  * Copyright (c) 2018, Linaro Limited
4  */
5 
6 #include <arm.h>
7 #include <console.h>
8 #include <drivers/gic.h>
9 #include <drivers/pl011.h>
10 #include <io.h>
11 #include <kernel/generic_boot.h>
12 #include <kernel/interrupt.h>
13 #include <kernel/misc.h>
14 #include <kernel/panic.h>
15 #include <kernel/pm_stubs.h>
16 #include <kernel/thread.h>
17 #include <kernel/timer.h>
18 #include <mm/core_memprot.h>
19 #include <platform_config.h>
20 #include <rng_pta.h>
21 #include <sm/optee_smc.h>
22 #include <tee/entry_fast.h>
23 #include <tee/entry_std.h>
24 
25 static const struct thread_handlers handlers = {
26 	.cpu_on = cpu_on_handler,
27 	.cpu_off = pm_do_nothing,
28 	.cpu_suspend = pm_do_nothing,
29 	.cpu_resume = pm_do_nothing,
30 	.system_off = pm_do_nothing,
31 	.system_reset = pm_do_nothing,
32 };
33 
34 static struct gic_data gic_data;
35 static struct pl011_data console_data;
36 
37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
38 			CORE_MMU_PGDIR_SIZE);
39 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
40 register_phys_mem_pgdir(MEM_AREA_IO_SEC, THERMAL_SENSOR_BASE,
41 			CORE_MMU_PGDIR_SIZE);
42 
43 const struct thread_handlers *generic_boot_get_handlers(void)
44 {
45 	return &handlers;
46 }
47 
48 void itr_core_handler(void)
49 {
50 	gic_it_handle(&gic_data);
51 }
52 
53 void console_init(void)
54 {
55 	pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ,
56 		   CONSOLE_BAUDRATE);
57 	register_serial_console(&console_data.chip);
58 }
59 
60 void main_init_gic(void)
61 {
62 	vaddr_t gicd_base;
63 
64 	gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET,
65 					  MEM_AREA_IO_SEC);
66 
67 	if (!gicd_base)
68 		panic();
69 
70 	/* On ARMv8-A, GIC configuration is initialized in TF-A */
71 	gic_init_base_addr(&gic_data, 0, gicd_base);
72 
73 	itr_init(&gic_data.chip);
74 }
75 
76 static enum itr_return timer_itr_cb(struct itr_handler *h __unused)
77 {
78 	/* Reset timer for next FIQ */
79 	generic_timer_handler(TIMER_PERIOD_MS);
80 
81 	/* Collect entropy on each timer FIQ */
82 	rng_collect_entropy();
83 
84 	return ITRR_HANDLED;
85 }
86 
87 static struct itr_handler timer_itr = {
88 	.it = IT_SEC_TIMER,
89 	.flags = ITRF_TRIGGER_LEVEL,
90 	.handler = timer_itr_cb,
91 };
92 
93 static TEE_Result init_timer_itr(void)
94 {
95 	itr_add(&timer_itr);
96 	itr_enable(IT_SEC_TIMER);
97 
98 	/* Enable timer FIQ to fetch entropy required during boot */
99 	generic_timer_start(TIMER_PERIOD_MS);
100 
101 	return TEE_SUCCESS;
102 }
103 driver_init(init_timer_itr);
104