1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2013, ARM Ltd 4 * Copyright (c) 2014, Allwinner Technology Co., Ltd. 5 * Copyright (c) 2018, Linaro Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <compiler.h> 32 #include <console.h> 33 #include <io.h> 34 #include <stdint.h> 35 #include <kernel/boot.h> 36 #include <kernel/misc.h> 37 #include <kernel/panic.h> 38 #include <kernel/delay.h> 39 #include <mm/core_mmu.h> 40 #include <mm/core_memprot.h> 41 #include <mm/tee_pager.h> 42 #include <platform_config.h> 43 #include <sm/optee_smc.h> 44 #include <sm/psci.h> 45 #include <arm32.h> 46 47 #define REG_CPUCFG_RES0 (0x0000) 48 #define REG_CPUCFG_CPU_RST(cpu) (0x0040 + (cpu) * (0x0040)) 49 #define REG_CPUCFG_GEN_CTRL (0x0184) 50 #define REG_CPUCFG_PRIV0 (0x01a4) 51 #define REG_CPUCFG_DBG_CTRL1 (0x01e4) 52 #define REG_PRCM_CPU_PWROFF (0x0100) 53 #define REG_PRCM_CPU_PWR_CLAMP(cpu) (0x0140 + (cpu) * (0x0004)) 54 55 int psci_features(uint32_t psci_fid) 56 { 57 switch (psci_fid) { 58 #ifdef CFG_BOOT_SECONDARY_REQUEST 59 case PSCI_CPU_ON: 60 return 0; 61 #endif 62 63 default: 64 return PSCI_RET_NOT_SUPPORTED; 65 } 66 } 67 68 #ifdef CFG_BOOT_SECONDARY_REQUEST 69 int psci_cpu_on(uint32_t core_idx, uint32_t entry, 70 uint32_t context_id) 71 { 72 vaddr_t base = (vaddr_t)phys_to_virt(SUNXI_PRCM_BASE, MEM_AREA_IO_SEC, 73 SUNXI_PRCM_REG_SIZE); 74 vaddr_t cpucfg = (vaddr_t)phys_to_virt(SUNXI_CPUCFG_BASE, 75 MEM_AREA_IO_SEC, 76 SUNXI_CPUCFG_REG_SIZE); 77 uint32_t tmpff; 78 uint32_t val; 79 80 assert(base); 81 assert(cpucfg); 82 83 if ((core_idx == 0) || (core_idx >= CFG_TEE_CORE_NB_CORE)) 84 return PSCI_RET_INVALID_PARAMETERS; 85 86 /* set secondary cores' NS entry addresses */ 87 boot_set_core_ns_entry(core_idx, entry, context_id); 88 89 val = virt_to_phys((void *)TEE_LOAD_ADDR); 90 91 /* set entry address */ 92 DMSG("set entry address for CPU %d", core_idx); 93 io_write32(cpucfg + REG_CPUCFG_PRIV0, val); 94 95 /* assert reset on target CPU */ 96 DMSG("assert reset on target CPU %d", core_idx); 97 io_write32(cpucfg + REG_CPUCFG_CPU_RST(core_idx), 0); 98 99 /* invalidate L1 cache */ 100 DMSG("invalidate L1 cache for CPU %d", core_idx); 101 io_clrbits32(cpucfg + REG_CPUCFG_GEN_CTRL, BIT32(core_idx)); 102 103 /* lock CPU (Disable external debug access) */ 104 DMSG("lock CPU %d", core_idx); 105 io_clrbits32(cpucfg + REG_CPUCFG_DBG_CTRL1, BIT32(core_idx)); 106 107 /* release clamp */ 108 DMSG("release clamp for CPU %d", core_idx); 109 tmpff = 0x1ff; 110 do { 111 tmpff >>= 1; 112 io_write32(base + REG_PRCM_CPU_PWR_CLAMP(core_idx), tmpff); 113 } while (tmpff); 114 mdelay(10); 115 116 /* clear power gating */ 117 DMSG("clear power gating for CPU %d", core_idx); 118 io_clrbits32(base + REG_PRCM_CPU_PWROFF, BIT32(core_idx)); 119 udelay(1000); 120 121 /* de-assert reset on target CPU */ 122 DMSG("de-assert reset on target CPU %d", core_idx); 123 io_write32(cpucfg + REG_CPUCFG_CPU_RST(core_idx), 0x03); 124 125 /* unlock CPU (enable external debug access) */ 126 DMSG("unlock CPU %d", core_idx); 127 io_setbits32(cpucfg + REG_CPUCFG_DBG_CTRL1, BIT32(core_idx)); 128 129 return PSCI_RET_SUCCESS; 130 } 131 132 int __noreturn psci_cpu_off(void) 133 { 134 uint32_t core_id; 135 vaddr_t base = (vaddr_t)phys_to_virt(SUNXI_PRCM_BASE, MEM_AREA_IO_SEC, 136 SUNXI_PRCM_REG_SIZE); 137 vaddr_t cpucfg = (vaddr_t)phys_to_virt(SUNXI_CPUCFG_BASE, 138 MEM_AREA_IO_SEC, 139 SUNXI_CPUCFG_REG_SIZE); 140 141 core_id = get_core_pos(); 142 143 DMSG("core_id: %" PRIu32, core_id); 144 145 #ifdef CFG_PSCI_ARM32 146 psci_armv7_cpu_off(); 147 #endif /* CFG_PSCI_ARM32 */ 148 149 assert(base); 150 assert(cpucfg); 151 152 /* set power gating */ 153 DMSG("set power gating for cpu %d", core_id); 154 io_setbits32(base + REG_PRCM_CPU_PWROFF, BIT32(core_id)); 155 156 /* Activate power clamp */ 157 DMSG("Activate power clamp for cpu %d", core_id); 158 io_write32(base + REG_PRCM_CPU_PWR_CLAMP(core_id), 0xff); 159 160 while (true) 161 wfi(); 162 } 163 #endif 164