1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2014, Allwinner Technology Co., Ltd. 4 * Copyright (c) 2018, Linaro Limited 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <console.h> 31 #include <io.h> 32 #include <stdint.h> 33 #include <drivers/gic.h> 34 #include <drivers/serial8250_uart.h> 35 #include <kernel/generic_boot.h> 36 #include <kernel/misc.h> 37 #include <kernel/panic.h> 38 #include <kernel/pm_stubs.h> 39 #include <kernel/tz_ssvce_def.h> 40 #include <mm/core_mmu.h> 41 #include <mm/core_memprot.h> 42 #include <mm/tee_pager.h> 43 #include <platform_config.h> 44 #include <sm/tee_mon.h> 45 #include <sm/optee_smc.h> 46 #include <tee/entry_fast.h> 47 #include <tee/entry_std.h> 48 #include <arm32.h> 49 50 #ifdef GIC_BASE 51 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE); 52 #endif 53 54 #ifdef CONSOLE_UART_BASE 55 register_phys_mem(MEM_AREA_IO_NSEC, 56 CONSOLE_UART_BASE, SUNXI_UART_REG_SIZE); 57 #endif 58 59 #ifdef SUNXI_TZPC_BASE 60 register_phys_mem(MEM_AREA_IO_SEC, SUNXI_TZPC_BASE, SUNXI_TZPC_REG_SIZE); 61 #define REG_TZPC_SMTA_DECPORT0_STA_REG (0x0004) 62 #define REG_TZPC_SMTA_DECPORT0_SET_REG (0x0008) 63 #define REG_TZPC_SMTA_DECPORT0_CLR_REG (0x000C) 64 #define REG_TZPC_SMTA_DECPORT1_STA_REG (0x0010) 65 #define REG_TZPC_SMTA_DECPORT1_SET_REG (0x0014) 66 #define REG_TZPC_SMTA_DECPORT1_CLR_REG (0x0018) 67 #define REG_TZPC_SMTA_DECPORT2_STA_REG (0x001c) 68 #define REG_TZPC_SMTA_DECPORT2_SET_REG (0x0020) 69 #define REG_TZPC_SMTA_DECPORT2_CLR_REG (0x0024) 70 #endif 71 72 #ifdef SUNXI_CPUCFG_BASE 73 register_phys_mem(MEM_AREA_IO_SEC, SUNXI_CPUCFG_BASE, SUNXI_CPUCFG_REG_SIZE); 74 #endif 75 76 #ifdef SUNXI_PRCM_BASE 77 register_phys_mem(MEM_AREA_IO_SEC, SUNXI_PRCM_BASE, SUNXI_PRCM_REG_SIZE); 78 #endif 79 80 static struct gic_data gic_data; 81 static void tzpc_init(void); 82 83 static void main_fiq(void) 84 { 85 panic(); 86 } 87 88 static const struct thread_handlers handlers = { 89 .std_smc = tee_entry_std, 90 .fast_smc = tee_entry_fast, 91 .nintr = main_fiq, 92 .cpu_on = pm_panic, 93 .cpu_off = pm_panic, 94 .cpu_suspend = pm_panic, 95 .cpu_resume = pm_panic, 96 .system_off = pm_panic, 97 .system_reset = pm_panic, 98 }; 99 100 static struct serial8250_uart_data console_data; 101 102 const struct thread_handlers *generic_boot_get_handlers(void) 103 { 104 return &handlers; 105 } 106 107 void console_init(void) 108 { 109 #ifdef CFG_SUN8I_H2_PLUS 110 serial8250_uart_init(&console_data, 111 CONSOLE_UART_BASE, 112 CONSOLE_UART_CLK_IN_HZ, 113 CONSOLE_BAUDRATE); 114 register_serial_console(&console_data.chip); 115 #endif 116 } 117 118 #ifdef SUNXI_TZPC_BASE 119 static void tzpc_init(void) 120 { 121 vaddr_t tzpc; 122 123 tzpc = (vaddr_t)phys_to_virt(SUNXI_TZPC_BASE, MEM_AREA_IO_SEC); 124 125 DMSG("SMTA_DECPORT0=%x", read32(tzpc + REG_TZPC_SMTA_DECPORT0_STA_REG)); 126 DMSG("SMTA_DECPORT1=%x", read32(tzpc + REG_TZPC_SMTA_DECPORT1_STA_REG)); 127 DMSG("SMTA_DECPORT2=%x", read32(tzpc + REG_TZPC_SMTA_DECPORT2_STA_REG)); 128 129 /* Allow all peripherals for normal world */ 130 write32(0xbe, tzpc + REG_TZPC_SMTA_DECPORT0_SET_REG); 131 write32(0xff, tzpc + REG_TZPC_SMTA_DECPORT1_SET_REG); 132 write32(0x7f, tzpc + REG_TZPC_SMTA_DECPORT2_SET_REG); 133 134 DMSG("SMTA_DECPORT0=%x", read32(tzpc + REG_TZPC_SMTA_DECPORT0_STA_REG)); 135 DMSG("SMTA_DECPORT1=%x", read32(tzpc + REG_TZPC_SMTA_DECPORT1_STA_REG)); 136 DMSG("SMTA_DECPORT2=%x", read32(tzpc + REG_TZPC_SMTA_DECPORT2_STA_REG)); 137 } 138 #else 139 static inline void tzpc_init(void) 140 { 141 } 142 #endif /* SUNXI_TZPC_BASE */ 143 144 void main_init_gic(void) 145 { 146 vaddr_t gicc_base; 147 vaddr_t gicd_base; 148 149 gicc_base = core_mmu_get_va(GIC_BASE + GICC_OFFSET, MEM_AREA_IO_SEC); 150 gicd_base = core_mmu_get_va(GIC_BASE + GICD_OFFSET, MEM_AREA_IO_SEC); 151 152 if (!gicc_base || !gicd_base) 153 panic(); 154 155 /* Initialize GIC */ 156 gic_init(&gic_data, gicc_base, gicd_base); 157 itr_init(&gic_data.chip); 158 } 159 160 void main_secondary_init_gic(void) 161 { 162 gic_cpu_init(&gic_data); 163 } 164 165 void plat_cpu_reset_late(void) 166 { 167 assert(!cpu_mmu_enabled()); 168 169 if (get_core_pos()) 170 return; 171 172 tzpc_init(); 173 } 174